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TLV75712PDYDR

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TLV75712PDYDR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TLV75712PDYDR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin (1.45V to 5.5V operating range); a capacitor of 1µF or larger is required from this pin to ground.
2 GND power_in Ground pin.
3 EN input Enable pin: drive EN greater than VHI to turn on the regulator, and less than VLO to place the LDO into shutdown mode.
4 NC unconnected No internal connection.
5 OUT power_out Regulated output voltage pin; a capacitor of 1µF or larger is required from this pin to ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN 1.45 5.5 V 5
Output accuracy VOUT -1 1 % -40°C ≤ TJ ≤ 85°C, VOUT ≥ 1V 5
Output accuracy VOUT -1.5 1.5 % VOUT ≥ 1V 5
Line regulation ΔVOUT/ΔVIN 2 mV VOUT + 0.5V ≤ VIN ≤ 5.5V 5
Load regulation ΔVOUT/ΔIOUT 0.069 V/A 0.1 mA ≤ IOUT ≤ 1A, VIN ≥ 2.4V DYD package 5
Ground current IGND 25 31 µA TJ = 25°C 5
Ground current IGND 33 µA -40°C ≤ TJ ≤ +85°C 5
Ground current IGND 40 µA -40°C ≤ TJ ≤ +125°C 5
Shutdown current ISHDN 0.1 1 µA VEN ≤ 0.4V, 1.45V ≤ VIN ≤ 5.5V 5
Output current limit ICL 1.2 1.55 1.78 A VIN = VOUT + VDO(MAX) + 0.25V, VOUT = VOUT - 0.2V, VOUT ≤ 1.5V 5
Short circuit current limit ISC 755 mA VOUT = 0V, VIN = VOUT + VDO(MAX) + 0.25V 5
Dropout voltage VDO 1025 1075 mV IOUT = 1A, -40°C ≤ TJ ≤ +85°C, 1.2V ≤ VOUT < 1.5V, DYD package 6
Dropout voltage VDO 1125 mV IOUT = 1A, -40°C ≤ TJ ≤ +125°C, 1.2V ≤ VOUT < 1.5V, DYD package 6
Power supply rejection ratio PSRR 52 dB f = 1kHz, VIN = VOUT + 1V, IOUT = 50mA 6
Power supply rejection ratio PSRR 46 dB f = 100kHz, VIN = VOUT + 1 V, IOUT = 50mA 6
Output noise voltage Vn 71.5 µVRMS BW = 10Hz to 100kHz, VOUT = 1.2V, IOUT = 1A 6
Undervoltage lockout VUVLO 1.21 1.3 1.44 V VIN rising 6
Undervoltage lockout hysteresis VUVLO,HYST 40 mV VIN falling 6
Startup time tSTR 550 µs 6
EN pin high voltage (enabled) VHI 1 V 6
EN pin low voltage VLO 0.3 V 6
Enable pin current IEN 10 nA VIN = 5.5V, EN = 5.5V 6
Pulldown resistance RPULLDOWN 95 Ω VIN = 3.3V (P version only) 6
Thermal shutdown TSD 165 °C Shutdown, temperature increasing 6
Thermal shutdown reset TSD 155 °C Reset, temperature decreasing 6
Supply voltage VIN -0.3 6 V 4
Enable voltage VEN -0.3 6 V 4
Operating junction temperature range TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD HBM V(ESD) -1000 1000 V Human-body model per ANSI/ESDA/JEDEC JS-001 4
ESD CDM V(ESD) -500 500 V Charged-device model per JESD22-C101 4
Input voltage VIN 1.45 5.5 V 4
Enable voltage VEN 0 5.5 V 4
Output current IOUT 0 1 A 4
Input capacitor CIN 1 µF 4
Output capacitor COUT 1 200 µF 4
Enable toggle frequency fEN 10 kHz 4
Junction temperature TJ -40 125 °C 4
Junction-to-ambient thermal resistance RθJA 60.3 °C/W DYD, EVM 5
Junction-to-top characterization parameter ψJT 14.2 °C/W DYD, EVM 5
Junction-to-board characterization parameter ψJB 35.9 °C/W DYD, EVM 5
Junction-to-ambient thermal resistance RθJA 92.5 °C/W DYD, JEDEC 5
Junction-to-case (top) thermal resistance RθJC(top) 119.8 °C/W DYD, JEDEC 5
Junction-to-board thermal resistance RθJB 45.8 °C/W DYD, JEDEC 5
Junction-to-top characterization parameter ψJT 16.7 °C/W DYD, JEDEC 5
Junction-to-board characterization parameter ψJB 44.9 °C/W DYD, JEDEC 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 34.3 °C/W DYD, JEDEC 5

CAD (KiCad official)

  • Symbol: TLV75712PDYDR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv75712pdydr-etched.step / tlv75712pdydr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv75712pdydr.step / tlv75712pdydr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 239d1f1e9bce2703, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF