component
TLV75518PDYDR
Public Made by Adomby adom
Texas Instruments Others, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TLV75518PDYDR
Texas Instruments · Others · SOT-23-5
TLV75518PDYDR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input pin; a capacitor of 1µF or larger is required from this pin to ground. |
| 2 | GND | power_in | Ground pin, internally connected to the exposed thermal pad. |
| 3 | EN | input | Enable pin: drive EN greater than VHI to turn on the regulator and less than VLO to place the LDO into shutdown mode. |
| 4 | NC | unconnected | No internal connection. |
| 5 | OUT | power_out | Regulated output voltage pin; a capacitor of 1µF or larger is required from this pin to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Others |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 1.45 | 5.5 | V | 4 | ||
| Output voltage | VOUT | 0.6 | 5 | V | 4 | ||
| Enable voltage | VEN | 0 | 5.5 | V | 4 | ||
| Output current | IOUT | 0 | 500 | mA | 4 | ||
| Input capacitor | CIN | 1 | µF | 4 | |||
| Output capacitor | COUT | 1 | 200 | µF | 4 | ||
| Enable toggle frequency | fEN | 10 | kHz | 4 | |||
| Junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Supply voltage | VIN | -0.3 | 6 | V | 4 | ||
| Enable voltage | VEN | -0.3 | 6 | V | 4 | ||
| Output voltage | VOUT | -0.3 | V | Max is VIN + 0.3 V or 6.0 V, whichever is smaller | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Output accuracy | -1.5 | 1.5 | % | -40°C ≤ TJ ≤ +85°C; VOUT ≥ 1V | 5 | ||
| Ground current | IGND | 14 | 25 | 31 | µA | TJ = 25°C, IOUT = 0mA | 5 |
| Ground current | IGND | 33 | µA | -40°C ≤ TJ ≤ +85°C, IOUT = 0mA | 5 | ||
| Ground current | IGND | 40 | µA | -40°C ≤ TJ ≤ +125°C, IOUT = 0mA | 5 | ||
| Shutdown current | ISHDN | 0.1 | 1 | µA | VEN ≤ 0.4V, 1.4V ≤ VIN ≤ 5.5V, -40°C ≤ TJ ≤ +125°C | 5 | |
| Output current limit | ICL | 560 | 720 | 865 | mA | VOUT = 0.9 x VOUT, 1.5V < VOUT ≤ 4.5V | 5 |
| Short-circuit current limit | ISC | 355 | mA | VOUT = 0V | 5 | ||
| Dropout voltage | VDO | 325 | 400 | mV | IOUT = 500mA, -40°C ≤ TJ ≤ +85°C; 1.8V ≤ VOUT < 2.5V, DYD package | 6 | |
| Dropout voltage | VDO | 420 | mV | IOUT = 500mA, -40°C ≤ TJ ≤ +125°C; 1.8V ≤ VOUT < 2.5V, DYD package | 6 | ||
| Undervoltage lockout | VUVLO | 1.21 | 1.3 | 1.44 | V | VIN rising | 6 |
| Junction-to-ambient thermal resistance (JEDEC) | RθJA | 92.5 | °C/W | JEDEC standard PCB, DYD (SOT-23-5) | 5 | ||
| Junction-to-ambient thermal resistance (EVM) | RθJA | 60.3 | °C/W | EVM, DYD (SOT-23-5) | 5 |
CAD (KiCad official)
- Symbol:
TLV75518PDYDR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tlv75518pdydr-etched.step/tlv75518pdydr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv75518pdydr.step/tlv75518pdydr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
96e2706d4b13656d, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TLV75518PDYDR
**Texas Instruments** · Others · SOT-23-5
TLV75518PDYDR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input pin; a capacitor of 1µF or larger is required from this pin to ground. |
| 2 | GND | power_in | Ground pin, internally connected to the exposed thermal pad. |
| 3 | EN | input | Enable pin: drive EN greater than VHI to turn on the regulator and less than VLO to place the LDO into shutdown mode. |
| 4 | NC | unconnected | No internal connection. |
| 5 | OUT | power_out | Regulated output voltage pin; a capacitor of 1µF or larger is required from this pin to ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Others |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 1.45 | | 5.5 | V | | 4 |
| Output voltage | VOUT | 0.6 | | 5 | V | | 4 |
| Enable voltage | VEN | 0 | | 5.5 | V | | 4 |
| Output current | IOUT | 0 | | 500 | mA | | 4 |
| Input capacitor | CIN | 1 | | | µF | | 4 |
| Output capacitor | COUT | 1 | | 200 | µF | | 4 |
| Enable toggle frequency | fEN | | | 10 | kHz | | 4 |
| Junction temperature | TJ | -40 | | 125 | °C | | 4 |
| Supply voltage | VIN | -0.3 | | 6 | V | | 4 |
| Enable voltage | VEN | -0.3 | | 6 | V | | 4 |
| Output voltage | VOUT | -0.3 | | | V | Max is VIN + 0.3 V or 6.0 V, whichever is smaller | 4 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Output accuracy | | -1.5 | | 1.5 | % | -40°C ≤ TJ ≤ +85°C; VOUT ≥ 1V | 5 |
| Ground current | IGND | 14 | 25 | 31 | µA | TJ = 25°C, IOUT = 0mA | 5 |
| Ground current | IGND | | | 33 | µA | -40°C ≤ TJ ≤ +85°C, IOUT = 0mA | 5 |
| Ground current | IGND | | | 40 | µA | -40°C ≤ TJ ≤ +125°C, IOUT = 0mA | 5 |
| Shutdown current | ISHDN | | 0.1 | 1 | µA | VEN ≤ 0.4V, 1.4V ≤ VIN ≤ 5.5V, -40°C ≤ TJ ≤ +125°C | 5 |
| Output current limit | ICL | 560 | 720 | 865 | mA | VOUT = 0.9 x VOUT, 1.5V < VOUT ≤ 4.5V | 5 |
| Short-circuit current limit | ISC | | | 355 | mA | VOUT = 0V | 5 |
| Dropout voltage | VDO | | 325 | 400 | mV | IOUT = 500mA, -40°C ≤ TJ ≤ +85°C; 1.8V ≤ VOUT < 2.5V, DYD package | 6 |
| Dropout voltage | VDO | | | 420 | mV | IOUT = 500mA, -40°C ≤ TJ ≤ +125°C; 1.8V ≤ VOUT < 2.5V, DYD package | 6 |
| Undervoltage lockout | VUVLO | 1.21 | 1.3 | 1.44 | V | VIN rising | 6 |
| Junction-to-ambient thermal resistance (JEDEC) | RθJA | | 92.5 | | °C/W | JEDEC standard PCB, DYD (SOT-23-5) | 5 |
| Junction-to-ambient thermal resistance (EVM) | RθJA | | 60.3 | | °C/W | EVM, DYD (SOT-23-5) | 5 |
## CAD (KiCad official)
- Symbol: `TLV75518PDYDR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tlv75518pdydr-etched.step` / `tlv75518pdydr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv75518pdydr.step` / `tlv75518pdydr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tlv755p.pdf?ts=1711517340379&ref_url=https%253A%252F%252Fwww.ti.com.cn%252Fproduct%252Fcn%252FTLV755P) (51 pp, sha256 `96e2706d4b13656d`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tlv75518pdydr-datasheet.pdf)