component
TLV74330PDBVR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 13d ago |
| viewers | 13d ago |
| package.json | 13d ago |
| page.json | 13d ago |
| README.md | 13d ago |
| tlv74330pdbvr-etched.glb | 13d ago |
| tlv74330pdbvr-etched.step | 13d ago |
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| tlv74330pdbvr-hero.overlay.json | 13d ago |
| tlv74330pdbvr.glb | 13d ago |
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| tlv74330pdbvr.step | 13d ago |
TLV74330PDBVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TLV74330PDBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input pin; a small capacitor is recommended from this pin to ground, and the recommended input voltage range is 1.4 V to 5.5 V. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Enable pin; drive EN greater than VEN(LO) to turn the regulator on, and less than VEN(LO) to put the LDO into shutdown mode. |
| 4 | NC | unconnected | No internal connection. |
| 5 | OUT | power_out | Regulated output voltage pin; for best transient response, use a small 1-µF ceramic capacitor from this pin to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 1.4 | 5.5 | V | 6 | ||
| DC output accuracy | -1 | 1 | % | TJ = 25°C | 6 | ||
| DC output accuracy | -1.4 | 1.4 | % | -40°C ≤ TJ ≤ 125°C | 6 | ||
| Undervoltage lockout, VIN rising | UVLO | 1.3 | 1.4 | V | VIN rising | 6 | |
| Undervoltage lockout, VIN falling | UVLO | 1.25 | V | VIN falling | 6 | ||
| Load regulation | ΔVO(ΔIO) | 16 | 25 | mV | ΔIO = 1 mA to 300 mA, DBV package | 6 | |
| Dropout voltage | VDO | 260 | mV | VOUT = 0.98 × VOUT(nom), IOUT = 300 mA, 2.5 V ≤ VOUT < 3.3 V, -40°C ≤ TJ ≤ 85°C | 6 | ||
| Dropout voltage | VDO | 290 | mV | VOUT = 0.98 × VOUT(nom), IOUT = 300 mA, 2.5 V ≤ VOUT < 3.3 V, -40°C ≤ TJ ≤ 125°C | 6 | ||
| Ground pin current | IGND | 34 | 60 | µA | IOUT = 0 mA | 6 | |
| Shutdown current | ISHDN | 0.1 | 1 | µA | VEN ≤ 0.35 V, 2 V ≤ VIN ≤ 5.5 V, TJ = 25°C | 6 | |
| EN pin high voltage (enabled) | VEN(HI) | 0.9 | V | 6 | |||
| EN pin low voltage (disabled) | VEN(LO) | 0.35 | V | 6 | |||
| Output current limit | ILIM | 360 | 700 | mA | 7 | ||
| Thermal shutdown | Tsd | 160 | °C | Shutdown, temperature increasing | 7 | ||
| Thermal shutdown reset | Tsd | 140 | °C | Reset, temperature decreasing | 7 | ||
| Line regulation | ΔVO(ΔVI) | 1 | mV | ΔVI = VIN(nom) to VIN(nom) + 1 | 6 | ||
| EN pin current | IEN | 0.01 | µA | VEN = 5.5 V | 6 | ||
| Pulldown resistor | 120 | Ω | VIN = 2.3 V | 7 | |||
| Input voltage range | VIN | 1.4 | 5.5 | V | 5 | ||
| Output voltage range | VOUT | 1 | 3.3 | V | 5 | ||
| Output current | IOUT | 0 | 300 | mA | 5 | ||
| Enable range | VEN | 0 | V | Maximum is VIN | 5 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Input voltage | VIN | -0.3 | 6 | V | All voltages with respect to GND | 5 | |
| Enable voltage | VEN | -0.3 | V | Maximum is VIN + 0.3 V | 5 | ||
| Output voltage | VOUT | -0.3 | 3.6 | V | All voltages with respect to GND | 5 | |
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 160 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 228.4 | °C/W | DBV (SOT-23) 5-pin | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 151.5 | °C/W | DBV (SOT-23) 5-pin | 5 | ||
| Junction-to-board thermal resistance | RθJB | 55.8 | °C/W | DBV (SOT-23) 5-pin | 5 | ||
| Junction-to-top characterization parameter | ψJT | 31.4 | °C/W | DBV (SOT-23) 5-pin | 5 | ||
| Junction-to-board characterization parameter | ψJB | 54.8 | °C/W | DBV (SOT-23) 5-pin | 5 |
CAD (KiCad official)
- Symbol:
TLV74330PDBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tlv74330pdbvr-etched.step/tlv74330pdbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv74330pdbvr.step/tlv74330pdbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (40 pp, sha256
b0f2e65e0aca7423, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).