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TLV713185PDBVT

Public Made by Adom

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tlv713185pdbvtfactory-2.0.0extractor-text

Verified TLV713185PDBVT

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 5 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TLV713185PDBVT · SOT-23-5 · 5 pins
  • ✓copper: 5 copper pads, none touching another net
  • ✓datasheet: all 5 pin names found in the 39-page datasheet
  • ✓distributor: lcsc C2877871, digikey 296-TLV713185PDBVTTR-ND, mouser 595-TLV713185PDBVT
  • ✓family: SOT-23-5
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-w715t533/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 5 pins = 5 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 5 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tlv713185pdbvt.kicad_sym✓ tlv713185pdbvt.kicad_mod✓ tlv713185pdbvt.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 16h ago
viewers tlv713185pdbvt: viewers · Ray 16h ago
package.json Publish 0.1.0 · Ray 16h ago
page.json Set visibility: public · Ray 16h ago
README.md Publish 0.1.0 · Ray 16h ago
tlv713185pdbvt-etched.glb Publish 0.1.0 · Ray 16h ago
tlv713185pdbvt-etched.step tlv713185pdbvt: factory component page (tier=mfr) · Ray 16h ago
tlv713185pdbvt-hero.glb tlv713185pdbvt: hero GLB from the etched model (keeps the MPN mark) · Ray 16h ago
tlv713185pdbvt-hero.overlay.json Publish 0.1.0 · Ray 16h ago
tlv713185pdbvt.glb Publish 0.1.0 · Ray 16h ago
tlv713185pdbvt.kicad_mod Publish 0.1.0 · Ray 16h ago
tlv713185pdbvt.kicad_sym Publish 0.1.0 · Ray 16h ago
tlv713185pdbvt.lbr Publish 0.1.0 · Ray 16h ago
tlv713185pdbvt.step Publish 0.1.0 · Ray 16h ago
verification.json Verified: Published by the parts factory: tier mfr, 5 pins · Ray 16h ago

TLV713185PDBVT

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TLV713185PDBVT from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN input Input pin with an input voltage range of 1.4 V to 5.5 V; a small capacitor is recommended from this pin to ground.
2 GND power_in Ground pin; the thermal pad on the X2SON package is tied to this node, but the SOT-23 package has no separate thermal pad.
3 EN input Driving EN above 0.9 V turns on the regulator, and driving EN below 0.4 V puts the regulator into shutdown mode.
4 NC unconnected No internal connection.
5 OUT output Regulated output voltage pin; a small 1-μF ceramic capacitor is recommended from this pin to ground for best transient response.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN 1.4 5.5 V 6
Output current IOUT 0 150 mA 6
Input capacitor CIN 0 1 µF 6
Output capacitor COUT 0 0.1 100 µF 6
Operating junction temperature range TJ -40 125 °C 6
Input voltage absolute maximum VIN -0.3 6 V Over operating junction temperature range (TJ = 25°C); all voltages with respect to GND 6
Output voltage absolute maximum VOUT -0.3 3.6 V Over operating junction temperature range (TJ = 25°C); all voltages with respect to GND 6
Storage temperature Tstg -55 150 °C 6
Junction temperature absolute maximum TJ -55 125 °C Over operating junction temperature range (TJ = 25°C) 6
Output voltage range VOUT 1 3.3 V 7
DC output accuracy VOUT -1 1 % VOUT >= 1.8 V, TJ = 25°C 7
DC output accuracy VOUT -1.5 1.5 % VOUT >= 1.2 V, -40°C <= TJ <= 125°C 7
Line regulation ΔVOUT(ΔVIN) 1 5 mV Max {VOUT(nom) + 0.5 V, VIN = 2.0 V} <= VIN <= 5.5 V 7
Load regulation ΔVOUT(ΔIOUT) 10 30 mV 0 mA <= IOUT <= 150 mA 7
Dropout voltage VDO 350 575 mV VOUT = 0.98 × VOUT(nom), TJ = -40°C to 85°C; 1.8 V <= VOUT < 2.1 V, IOUT = 150 mA 7
Dropout voltage VDO 350 695 mV VOUT = 0.98 × VOUT(nom), TJ = -40°C to 125°C; 1.8 V <= VOUT < 2.1 V, IOUT = 150 mA 7
Dropout voltage VDO 70 mV VOUT = 0.98 × VOUT(nom), TJ = -40°C to 85°C; 1.8 V <= VOUT < 2.1 V, IOUT = 30 mA 7
Ground pin current IGND 50 75 µA IOUT = 0 mA 7
Shutdown current ISHUTDOWN 0.1 1 µA VEN <= 0.4 V, 2.0 V <= VIN <= 5.5 V, TJ = 25°C 7
Enable low (disabled) VLO 0 0.4 V 7
Output current limit ILIM 180 mA VIN = 2.25 V, VOUT = 1.8 V, TJ = -40 to 85°C 7
Thermal shutdown TSD 158 °C Shutdown, temperature increasing 7
Thermal shutdown reset TSD 140 °C Reset, temperature decreasing 7
Short-circuit current ISC 40 mA VOUT = 0 V 7
Power-supply rejection ratio PSRR 70 dB VIN = 3.3 V, VOUT = 2.8 V, IOUT = 30 mA, f = 100 Hz 7
Power-supply rejection ratio PSRR 55 dB VIN = 3.3 V, VOUT = 2.8 V, IOUT = 30 mA, f = 10 kHz 7
Output noise voltage Vn 73 µVRMS BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA 7
Start-up time tSTR 100 µs COUT = 1.0 µF, IOUT = 150 mA 7
Enable pin current IEN 0.01 µA EN = 5.5 V 7
Pulldown resistor (TLV713P only) RPULLDOWN 120 Ω VIN = 4 V 7
Junction-to-ambient thermal resistance (DBV) RθJA 249 °C/W DBV (SOT23), 5 pins 6
Junction-to-case (top) thermal resistance (DBV) RθJC(top) 172.7 °C/W DBV (SOT23), 5 pins 6
Junction-to-board thermal resistance (DBV) RθJB 76.7 °C/W DBV (SOT23), 5 pins 6
Junction-to-top characterization parameter (DBV) ψJT 49.7 °C/W DBV (SOT23), 5 pins 6
Junction-to-board characterization parameter (DBV) ψJB 75.8 °C/W DBV (SOT23), 5 pins 6

CAD (KiCad official)

  • Symbol: TLV713185PDBVT
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv713185pdbvt-etched.step / tlv713185pdbvt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv713185pdbvt.step / tlv713185pdbvt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 dc2f2e301f114fbe, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF