component
TLV7103318QDSERQ1
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6(1.5x1.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTLV7103318QDSERQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6(1.5x1.5)
TLV7103318QDSERQ1 from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN1 | input | Enable pin for regulator 1: driving EN1 over 0.9 V turns on regulator 1, and driving it below 0.4 V puts regulator 1 into shutdown mode. |
| 2 | IN | power_in | Input pin: a small capacitor is needed from this pin to ground to assure stability. |
| 3 | EN2 | input | Enable pin for regulator 2: driving EN2 over 0.9 V turns on regulator 2, and driving it below 0.4 V puts regulator 2 into shutdown mode. |
| 4 | GND | power_in | Ground pin. |
| 5 | OUT2 | power_out | Regulated output voltage pin for channel 2: a small 1 µF ceramic capacitor is needed from this pin to ground to assure stability. |
| 6 | OUT1 | power_out | Regulated output voltage pin for channel 1: a small 1 µF ceramic capacitor is needed from this pin to ground to assure stability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6(1.5x1.5) |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2 | 5.5 | V | 3 | ||
| Output voltage range | VO | 1.2 | 4.8 | V | 3 | ||
| DC output accuracy | VOUT | -2 | 2 | % | -40°C ≤ TA ≤ 125°C | 3 | |
| Load regulation | ΔVO/ΔIOUT | 5 | 15 | mV | 0 mA ≤ IOUT ≤ 200 mA | 3 | |
| Line regulation | ΔVO/ΔVIN | 1 | 5 | mV | VOUT(NOM) + 0.5 V ≤ VIN | 3 | |
| Dropout voltage | VDO | 140 | 200 | mV | VIN = 0.98 V × VOUT(NOM), IOUT = 200 mA, 3.3 V ≤ VOUT ≤ 4.8 V | 3 | |
| Output current limit | ICL | 220 | 350 | 550 | mA | VOUT = 0.9V × VOUT(NOM) | 3 |
| Quiescent current (both channels enabled) | IQ | 70 | 110 | µA | VEN1 = high, VEN2 = high, IOUT = 0 mA | 3 | |
| Shutdown current | ISHUTDOWN | 2.5 | 4 | μA | VEN1,2 ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V | 3 | |
| Operating ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Enable low (shutdown) | VLO | 0 | 0.4 | V | 4 | ||
| IN voltage | -0.3 | 6 | V | All voltages with respect to ground | 2 | ||
| EN voltage | -0.3 | V | 2 | ||||
| OUT voltage | -0.3 | 6 | V | All voltages with respect to ground | 2 | ||
| Operating ambient temperature (absolute maximum) | TA | -40 | 125 | °C | 2 | ||
| Junction temperature | TJ | 150 | °C | 2 | |||
| Storage temperature | Tstg | -55 | 150 | °C | 2 | ||
| Human-Body Model (HBM) ESD rating | 2 | kV | AEC-Q100 Classification Level H2 | 2 | |||
| Charged-Device Model (CDM) ESD rating | 750 | V | AEC-Q100 Classification Level C4B | 2 | |||
| Ground pin current | IGND | 360 | µA | IOUT1 = IOUT2 = 200mA | 3 | ||
| Quiescent current (OUT1 enabled, OUT2 off) | IQ | 35 | μA | VEN1 = high, VEN2 = low, IOUT1 = 0 mA | 3 | ||
| Quiescent current (OUT2 enabled, OUT1 off) | IQ | 35 | μA | VEN1 = low, VEN2 = high, IOUT2 = 0 mA | 3 | ||
| Power-supply rejection ratio | PSRR | 80 | dB | f = 10 Hz | 3 | ||
| Power-supply rejection ratio | PSRR | 75 | dB | f = 100 Hz | 3 | ||
| Power-supply rejection ratio | PSRR | 70 | dB | VOUT = 1.8 V, f = 1k Hz | 3 | ||
| Power-supply rejection ratio | PSRR | 50 | dB | f = 100 kHz | 3 | ||
| Output noise voltage | VN | 48 | μVRMS | BW = 100 Hz to 100 kHz, VOUT = 1.8 V | 3 | ||
| Startup time | tSTR | 100 | μs | COUT = 1 μF, IOUT = 200 mA | 3 | ||
| Enable pin current, enabled (base variant) | IEN | 0.04 | μA | TLV7103318-Q1, TLV7101828-Q1 | 4 | ||
| Undervoltage lockout | UVLO | 1.9 | V | VIN rising | 4 | ||
| Thermal shutdown temperature | TSD | 165 | °C | Shutdown, temperature increasing | 4 | ||
| Thermal shutdown reset temperature | TSD | 145 | °C | Reset, temperature decreasing | 4 | ||
| Junction-to-ambient thermal resistance | θJA | 190.5 | °C/W | DSE package, JESD51-2a environment, JEDEC high-K board, natural convection | 3 | ||
| Junction-to-case (top) thermal resistance | θJCtop | 94.9 | °C/W | DSE package | 3 | ||
| Junction-to-board thermal resistance | θJB | 149.3 | °C/W | DSE package | 3 | ||
| Junction-to-top characterization parameter | ψJT | 6.4 | °C/W | DSE package | 3 | ||
| Junction-to-board characterization parameter | ψJB | 152.8 | °C/W | DSE package | 3 |
CAD (KiCad official)
- Symbol:
TLV7103318QDSERQ1 - Footprint:
Package_SON:WSON-6_1.5x1.5mm_P0.5mm - 3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
- 3D model files:
tlv7103318qdserq1-etched.step/tlv7103318qdserq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv7103318qdserq1.step/tlv7103318qdserq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
6eb217813e37d697, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).