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TLV70436DBVR

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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page.json tlv70436dbvr: specified limits as data (metadata.characteristics, 33 rows from the datasheet) · Ray 17d ago
README.md tlv70436dbvr: specified limits as data (metadata.characteristics, 33 rows from the datasheet) · Ray 17d ago
tlv70436dbvr-etched.glb tlv70436dbvr: factory component page (tier=lcsc) · Ray 22d ago
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tlv70436dbvr-hero.glb tlv70436dbvr: hero GLB from the etched model (keeps the MPN mark) · Ray 22d ago
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TLV70436DBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TLV70436DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin.
2 IN input Input supply pin; a capacitor of 0.1 µF or larger is recommended from this pin to ground.
3 OUT output Regulator output; a capacitor of 1 µF or larger is required from this pin to ground, and the nominal output capacitance must be greater than 0.47 µF with effective capacitance above 0.47 µF at the pin.
4 NC unconnected Not internally connected; this pin can be left open or tied to ground for improved thermal performance.
5 NC unconnected Not internally connected; this pin can be left open or tied to ground for improved thermal performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 24 V TJ = 25°C 6
Output voltage range VOUT 1.2 5 V TJ = 25°C 6
DC output accuracy VOUT -2 2 % TJ = 25°C 6
Ground pin current (legacy chip) IGND 3.2 4.5 µA IOUT = 0 mA, TJ = 25°C 6
Ground pin current (legacy chip) IGND 3.2 5.5 µA IOUT = 100 mA, TJ = 25°C 6
Load regulation ΔVOUT (ΔIOUT) 10 mV VOUT < 3.3V, 0 < IOUT < 10 mA, TJ = 25°C 6
Load regulation ΔVOUT (ΔIOUT) 25 mV VOUT < 3.3V, 0 < IOUT < 50 mA, TJ = 25°C 6
Load regulation ΔVOUT (ΔIOUT) 33 50 mV VOUT < 3.3V, 0 < IOUT < 100 mA, TJ = 25°C 6
Load regulation ΔVOUT (ΔIOUT) 7 mV VOUT ≥ 3.3 V, 0 < IOUT < 10 mA, TJ = 25°C 6
Load regulation ΔVOUT (ΔIOUT) 35 mV VOUT ≥ 3.3 V, 0 < IOUT < 50 mA, TJ = 25°C 6
Load regulation ΔVOUT (ΔIOUT) 50 75 mV VOUT ≥ 3.3 V, 0 < IOUT < 100 mA, TJ = 25°C 6
Line regulation ΔVOUT (ΔVIN) 20 50 mV VOUT(NOM) + 1 V ≤ VIN ≤ 24 V, TJ = 25°C 6
Output current limit (legacy chip) ICL 160 1000 mA VOUT = 0 V, TJ = 25°C 6
Power-supply ripple rejection PSRR 60 dB f = 100 kHz, COUT = 10 µF 6
Dropout voltage VDO 75 mV VIN = VOUT(nom) – 0.1 V, IOUT = 10 mA, TJ = 25°C 6
Dropout voltage VDO 400 mV VIN = VOUT(nom) – 0.1 V, IOUT = 50 mA, TJ = 25°C 6
Dropout voltage VDO 850 1100 mV VIN = VOUT(nom) – 0.1 V, IOUT = 100 mA, TJ = 25°C 6
Operating junction temperature TJ -40 125 °C 6
Input voltage (absolute maximum, legacy chip) VIN -0.3 24 V Legacy chip only 4
Output voltage (absolute maximum, legacy chip) VOUT -0.3 5 V Legacy chip only 4
Junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
Input supply voltage VIN 2.5 24 V 5
Output voltage VOUT 1.205 5 V 5
Output current IOUT 0 150 mA 5
Input capacitor CIN 0 0.047 µF 5
Output capacitor (legacy chip) COUT 0.47 1 µF 5
Operating junction temperature TJ -40 125 °C 5
Junction-to-ambient thermal resistance RθJA 213.1 °C/W Legacy chip, DBV (SOT-23) 5 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 110.9 °C/W Legacy chip, DBV (SOT-23) 5 pins 5
Junction-to-board thermal resistance RθJB 97.4 °C/W Legacy chip, DBV (SOT-23) 5 pins 5
Junction-to-top characterization parameter ψJT 22 °C/W Legacy chip, DBV (SOT-23) 5 pins 5
Junction-to-board characterization parameter ψJB 78.4 °C/W Legacy chip, DBV (SOT-23) 5 pins 5

CAD (KiCad official)

  • Symbol: TLV70436DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv70436dbvr-etched.step / tlv70436dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv70436dbvr.step / tlv70436dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 4e3d09609c7cbe65, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF