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TLV70212DBVR

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs tlv70212dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers tlv70212dbvr: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json tlv70212dbvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 17h ago
README.md tlv70212dbvr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
tlv70212dbvr-etched.fit.json tlv70212dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tlv70212dbvr-etched.glb tlv70212dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tlv70212dbvr-etched.step tlv70212dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tlv70212dbvr.glb Publish 0.1.0 · Ray 1mo ago
tlv70212dbvr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tlv70212dbvr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tlv70212dbvr.lbr Publish 0.1.0 · Ray 1mo ago
tlv70212dbvr.step Publish 0.1.0 · Ray 1mo ago

TLV70212DBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TLV70212DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin. Operates from 2 V to 5.5 V (absolute max 6 V). A small 1-µF ceramic capacitor to GND is recommended for stability and good transient performance.
2 GND power_in Ground reference pin. Ground pin current is typically 35 µA at no load and 370 µA at 300-mA load.
3 EN input Enable input. Driving EN above 0.9 V turns the regulator on; driving EN below 0.4 V puts the device in shutdown (I_SHDN ~ 1 µA). For TLV702P variants, the output is discharged through an internal 120-Ω pulldown when disabled. Absolute max 6 V.
4 NC unconnected No connection. This pin can be tied to ground to improve thermal dissipation.
5 OUT power_out Regulated output voltage pin (1.2 V nominal for TLV70212, ±2% accuracy, up to 300 mA). A 1-µF ceramic capacitor to GND is required for stability. Absolute max 6 V; output is internally current-limited (~500 mA typ).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TLV70212DBVR
  • TLV70212DBVRDBVT
  • TLV70212DBVRDSER
  • TLV70212DBVRDSET

CAD (KiCad official)

  • Symbol: TLV70212DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv70212dbvr-etched.step / tlv70212dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv70212dbvr.step / tlv70212dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 7180f650f8b37a47, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF