# TLV70133DBVR

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TLV70133DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated 3.3-V output. Requires a >= 1 µF (>= 0.47 µF acceptable) ceramic capacitor from this pin to GND for stability. Rated for up to 150 mA continuous load; internal current limit is 160 mA (min). |
| 2 | GND | power_in | Device ground reference. All voltages in the datasheet are referenced to this pin. Typical ground current is 3.2 µA at IOUT = 0 mA. |
| 3 | IN | power_in | Unregulated input voltage. Operating range 2.5 V to 24 V (absolute max 24 V, min -0.3 V). A bypass capacitor to GND is recommended for line-transient response. |
| 4 | NC | unconnected | No internal connection. May be left floating or tied to GND to improve thermal performance of the SOT23-5 package. |
| 5 | NC | unconnected | No internal connection. May be left floating or tied to GND to improve thermal performance of the SOT23-5 package. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | PMIC |
| Pins | 5 |

## Ordering variants

Same part, different packaging or reel option.

- `TLV70133DBVR`
- `TLV70133DBVRDBVT`

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range |  |  |  | 24 | V |  | 3 |
| Output voltage range | VO | 1.2 |  | 5 | V |  | 3 |
| DC output accuracy | VOUT | -2 |  | 2 | % |  | 3 |
| Line regulation | ΔVO for ΔVIN |  | 20 | 50 | mV | VOUT(NOM) + 1 V < VIN < 24 V | 3 |
| Load regulation | ΔVO for ΔIOUT |  | 29 | 50 | mV | 1 mA < IOUT < 100 mA | 3 |
| Load regulation | ΔVO for ΔIOUT |  | 6 |  | mV | 1 mA < IOUT < 10 mA | 3 |
| Load regulation | ΔVO for ΔIOUT |  | 19 |  | mV | 1 mA < IOUT < 50 mA | 3 |
| Dropout voltage | VDO |  | 75 |  | mV | IOUT = 10 mA | 3 |
| Dropout voltage | VDO |  | 400 |  | mV | IOUT = 50 mA | 3 |
| Output current limit | ICL | 160 |  | 1000 | mA | VOUT = 0 V | 3 |
| Ground pin current | IGND |  | 3.2 | 4.5 | µA | IOUT = 0 mA | 3 |
| Ground pin current | IGND |  | 3.4 | 5.5 | µA | IOUT = 100 mA | 3 |
| Power-supply rejection ratio | PSRR |  | 60 |  | dB | f = 100 kHz, COUT = 10 µF | 3 |
| Input voltage (IN) absolute maximum |  | -0.3 |  | 24 | V | All voltages with respect to network ground terminal | 2 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 2 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 2 |
| Electrostatic discharge, human body model (HBM) |  |  |  | 2 | kV | JESD22-A114A | 2 |
| Electrostatic discharge, charged device model (CDM) |  |  |  | 500 | V | JESD22-C101B.01 | 2 |
| Operating free-air temperature range |  | -40 |  | 125 | °C |  | 7 |
| Output capacitor | COUT | 1 |  |  | µF |  | 4 |
| Junction-to-ambient thermal resistance | θJA |  | 213.1 |  | °C/W |  | 2 |
| Junction-to-case (top) thermal resistance | θJCtop |  | 110.9 |  | °C/W |  | 2 |
| Junction-to-board thermal resistance | θJB |  | 97.4 |  | °C/W |  | 2 |
| Junction-to-top characterization parameter | ψJT |  | 22 |  | °C/W |  | 2 |
| Junction-to-board characterization parameter | ψJB |  | 78.4 |  | °C/W |  | 2 |

## CAD (KiCad official)

- Symbol: `TLV70133DBVR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tlv70133dbvr-etched.step` / `tlv70133dbvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv70133dbvr.step` / `tlv70133dbvr.glb` are the bare package body.

## 3D model downloads

Two STEP files. Same geometry, different body top:

| File | Size | Use it when |
|---|---|---|
| [`tlv70133dbvr.step`](tlv70133dbvr.step) | 85 KB | You want the bare part, or you mark your own boards. |
| [`tlv70133dbvr-etched.step`](tlv70133dbvr-etched.step) | 2.0 MB | You want the part with `TLV70133DBVR` already on it. |

The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 496 faces against 102 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tlv70133.pdf) (13 pp, sha256 `adf8d4fee309c0d6`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlv70133dbvr-datasheet.pdf)