component
TLV70130DBVR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 20d ago |
| viewers | 20d ago |
| package.json | 20d ago |
| page.json | 16d ago |
| README.md | 16d ago |
| tlv70130dbvr-etched.glb | 20d ago |
| tlv70130dbvr-etched.step | 20d ago |
| tlv70130dbvr-hero.glb | 20d ago |
| tlv70130dbvr-hero.overlay.json | 20d ago |
| tlv70130dbvr.glb | 20d ago |
| tlv70130dbvr.kicad_mod | 20d ago |
| tlv70130dbvr.kicad_sym | 20d ago |
| tlv70130dbvr.lbr | 20d ago |
| tlv70130dbvr.step | 20d ago |
TLV70130DBVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TLV70130DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulator output; a capacitor of 1 µF or larger is required from this pin to ground, and the effective capacitance at the pin must stay above 0.47 µF after derating. |
| 2 | GND | power_in | Ground pin. |
| 3 | IN | input | Input supply pin, with input voltage range 2.5 V to 24 V; a capacitor of 0.1 µF or larger from this pin to ground is recommended. |
| 4 | NC | unconnected | Not internally connected; can be left open or tied to ground for improved thermal performance. |
| 5 | NC | unconnected | Not internally connected; can be left open or tied to ground for improved thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 2.5 | 24 | V | Input supply voltage | 4 | |
| Output voltage | VOUT | 1.205 | 5 | V | Output voltage | 4 | |
| Output current | IOUT | 0 | 150 | mA | Output current | 4 | |
| Input capacitor | CIN | 0 | 0.047 | µF | Effective value recommended 0.047 µF per note 2 | 4 | |
| Output capacitor (legacy chip) | COUT | 0.47 | 1 | µF | Legacy chip only; derates to 50% of nominal | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | Operating junction temperature | 4 | |
| Input voltage (legacy chip) | VIN | -0.3 | 24 | V | Legacy chip only; with respect to network ground | 4 | |
| Output voltage (legacy chip) | VOUT | -0.3 | 5 | V | Legacy chip only; with respect to network ground | 4 | |
| Junction temperature | TJ | -40 | 150 | °C | Absolute maximum | 4 | |
| Storage temperature | Tstg | -65 | 150 | °C | Absolute maximum | 4 | |
| Electrostatic discharge, human body model | V(ESD) | -2000 | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001, all pins | 4 | |
| Electrostatic discharge, charged device model | V(ESD) | -500 | 500 | V | CDM per JESD22-C101, all pins | 4 | |
| Ground pin current (legacy chip) | IGND | 3.2 | 4.5 | µA | IOUT = 0 mA, TJ = 25°C | 5 | |
| Ground pin current (legacy chip) | IGND | 3.2 | 5.5 | µA | IOUT = 100 mA, TJ = 25°C | 5 | |
| Line regulation | ΔVOUT(ΔVIN) | 20 | 50 | mV | VOUT(NOM) + 1 V ≤ VIN ≤ 24 V, TJ = 25°C | 5 | |
| Load regulation | ΔVOUT(ΔIOUT) | 29 | 50 | mV | 1 mA < IOUT < 100 mA | 5 | |
| DC output accuracy | VOUT | -2 | 2 | % | TJ = 25°C | 5 | |
| Output voltage range | VOUT | 1.2 | 5 | V | TJ = 25°C | 5 | |
| Junction-to-ambient thermal resistance (legacy chip) | RθJA | 213.1 | °C/W | Legacy chip, DBV (SOT-23) 5 pins | 5 | ||
| Junction-to-case (top) thermal resistance (legacy chip) | RθJC(top) | 110.9 | °C/W | Legacy chip, DBV (SOT-23) 5 pins | 5 | ||
| Junction-to-board thermal resistance (legacy chip) | RθJB | 97.4 | °C/W | Legacy chip, DBV (SOT-23) 5 pins | 5 | ||
| Junction-to-top characterization parameter (legacy chip) | ψJT | 22 | °C/W | Legacy chip, DBV (SOT-23) 5 pins | 5 | ||
| Junction-to-board characterization parameter (legacy chip) | ψJB | 78.4 | °C/W | Legacy chip, DBV (SOT-23) 5 pins | 5 |
CAD (KiCad official)
- Symbol:
TLV70130DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tlv70130dbvr-etched.step/tlv70130dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv70130dbvr.step/tlv70130dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
6f392668ac34bcee, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).