component
TLV70033DDCT
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLV70033DDCT
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TLV70033DDCT from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input pin; a small, 1-μF ceramic capacitor is recommended from this pin to ground to assure stability and good transient performance. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Driving EN over 0.9 V turns on the regulator; driving EN below 0.4 V puts the regulator into shutdown mode and reduces operating current to 1 μA, nominal. |
| 4 | NC | unconnected | No connection; this pin can be tied to ground to improve thermal dissipation. |
| 5 | OUT | power_out | Regulated output voltage pin; a small, 1-μF ceramic capacitor is needed from this pin to ground to assure stability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2 | 5.5 | V | 6 | ||
| DC output accuracy | VOUT | -2 | 2 | % | -40°C ≤ TJ ≤ +125°C | 6 | |
| Line regulation | ΔVOUT(ΔVIN) | 1 | 5 | mV | VOUT(nom) + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA | 6 | |
| Load regulation | ΔVOUT(ΔIOUT) | 1 | 15 | mV | 0 mA ≤ IOUT ≤ 200 mA | 6 | |
| Output current limit | ICL | 220 | 860 | mA | VOUT = 0.9 × VOUT(nom) | 6 | |
| Ground pin current | IGND | 31 | 55 | μA | IOUT = 0 mA | 6 | |
| Ground pin current | IGND | 270 | μA | IOUT = 200 mA, VIN = VOUT + 0.5 V | 6 | ||
| Ground pin current (shutdown) | ISHDN | 400 | nA | VEN ≤ 0.4 V, VIN = 2 V | 6 | ||
| Ground pin current (shutdown) | ISHDN | 1 | 2 | μA | VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V | 6 | |
| Enable pin high (enabled) | VEN(high) | 0.9 | V | 6 | |||
| Enable pin low (disabled) | VEN(low) | 0 | 0.4 | V | 6 | ||
| Enable pin current | IEN | 0.04 | 0.5 | μA | VIN = VEN = 5.5 V | 6 | |
| Undervoltage lockout | UVLO | 1.9 | V | VIN rising | 6 | ||
| Thermal shutdown temperature | Tsd | 160 | °C | Shutdown, temperature increasing | 6 | ||
| Thermal shutdown temperature reset | Tsd | 140 | °C | Reset, temperature decreasing | 6 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 6 | ||
| Power-supply rejection ratio | PSRR | 68 | dB | VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 kHz | 6 | ||
| Output noise voltage | Vn | 48 | μVRMS | BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA | 6 | ||
| Start-up time | tSTR | 100 | μs | COUT = 1 μF, IOUT = 200 mA | 6 | ||
| Input voltage range (recommended) | VIN | 2 | 5.5 | V | 5 | ||
| Output voltage range (recommended) | VOUT | 1.2 | 4.8 | V | 5 | ||
| Output current (recommended) | IOUT | 0 | 200 | mA | 5 | ||
| Input voltage absolute maximum | VIN | -0.3 | 6 | V | 5 | ||
| Enable voltage absolute maximum | VEN | -0.3 | 6 | V | VEN absolute maximum rating is VIN + 0.3 V or 6 V, whichever is less | 5 | |
| Output voltage absolute maximum | VOUT | -0.3 | 6 | V | 5 | ||
| Operating junction temperature absolute maximum | TJ | -55 | 150 | °C | Operating junction temperature range | 5 | |
| Storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| Junction-to-ambient thermal resistance (DDC SOT) | RθJA | 235.9 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance (DDC SOT) | RθJC(top) | 61.9 | °C/W | 5 | |||
| Junction-to-board thermal resistance (DDC SOT) | RθJB | 54 | °C/W | 5 | |||
| Junction-to-top characterization parameter (DDC SOT) | ψJT | 0.8 | °C/W | 5 | |||
| Junction-to-board characterization parameter (DDC SOT) | ψJB | 53.4 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TLV70033DDCT - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tlv70033ddct-etched.step/tlv70033ddct-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv70033ddct.step/tlv70033ddct.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (42 pp, sha256
fdb008365c01d2be, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).