# TLV70025QDDCRQ1

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TLV70025QDDCRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Input pin; a small 1µF ceramic capacitor is recommended from this pin to ground to provide stability and good transient performance. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Enable pin; driving EN over 0.9V turns on the regulator, and driving EN below 0.4V puts the regulator into shutdown mode, reducing operating current to 1µA nominal. |
| 4 | NC | unconnected | No connection; this pin can be tied to ground to improve thermal dissipation. |
| 5 | OUT | output | Regulated output voltage pin; a small 1µF ceramic capacitor is needed from this pin to ground to provide stability. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2 |  | 5.5 | V |  | 5 |
| DC output accuracy | VOUT | -2 |  | 2 | % | -40°C ≤ TA ≤ +125°C, VOUT ≥ 1V | 5 |
| Line regulation | ΔVO/ΔVIN |  | 1 | 5 | mV | VOUT(NOM) + 0.5V ≤ VIN ≤ 5.5V, IOUT = 10mA | 5 |
| Load regulation | ΔVO/ΔIOUT |  | 15 |  | mV | 0mA ≤ IOUT ≤ 200mA | 5 |
| Dropout voltage | VDO |  | 175 | 250 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 200mA | 5 |
| Output current limit | ICL | 220 | 350 | 860 | mA | VOUT = 0.9 × VOUT(NOM) | 5 |
| Ground pin current | IGND |  | 31 | 55 | µA | IOUT = 0mA | 5 |
| Ground pin current | IGND |  | 270 |  | µA | IOUT = 200mA, VIN = VOUT + 0.5V | 5 |
| Ground pin current (shutdown) | ISHDN |  | 1 | 2.5 | µA | VEN ≤ 0.4V, 2.0V ≤ VIN ≤ 4.5V | 5 |
| Power-supply rejection ratio | PSRR |  | 68 |  | dB | VIN = 2.3V, VOUT = 1.8V, IOUT = 10mA, f = 1kHz | 5 |
| Output noise voltage | VN |  | 48 |  | µVRMS | BW = 100Hz to 100kHz, VIN = 2.3V, VOUT = 1.8V, IOUT = 10mA | 5 |
| Startup time | tSTR |  | 100 |  | µs | COUT = 1µF, IOUT = 200mA | 5 |
| Enable pin high (enabled) | VEN(HI) | 0.9 |  |  | V |  | 5 |
| Enable pin low (disabled) | VEN(LO) | 0 |  | 0.4 | V |  | 5 |
| Enable pin current | IEN |  | 0.04 | 0.5 | µA | VEN = 5.5V, IOUT = 10µA | 5 |
| Undervoltage lockout | UVLO |  | 1.9 |  | V | VIN rising | 5 |
| Thermal shutdown temperature | TSD |  | 160 |  | °C | Shutdown, temperature increasing | 5 |
| Thermal shutdown reset temperature | TSD |  | 140 |  | °C | Reset, temperature decreasing | 5 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 5 |
| Input voltage | VIN | -0.3 |  | 6 | V | All voltages with respect to GND | 4 |
| Enable voltage | VEN | -0.3 |  |  | V | Maximum is VIN + 0.3 V | 4 |
| Output voltage | VOUT | -0.3 |  | 6 | V | All voltages with respect to GND | 4 |
| Operating ambient temperature | TA | -40 |  | 150 | °C |  | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 4 |
| Input voltage | VIN | 2 |  | 5.5 | V |  | 4 |
| Enable voltage | VEN | 0 |  | 5.5 | V |  | 4 |
| Output current | IOUT |  |  | 200 | mA |  | 4 |
| Input capacitor | CIN | 0 |  | 1 | µF |  | 4 |
| Output capacitor | COUT | 0.22 |  | 1 | µF |  | 4 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 262.8 |  | °C/W | DDC (SOT) 5-pin package | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 68.2 |  | °C/W | DDC (SOT) 5-pin package | 4 |
| Junction-to-board thermal resistance | RθJB |  | 81.6 |  | °C/W | DDC (SOT) 5-pin package | 4 |
| Junction-to-top characterization parameter | ψJT |  | 1.1 |  | °C/W | DDC (SOT) 5-pin package | 4 |
| Junction-to-board characterization parameter | ψJB |  | 80.9 |  | °C/W | DDC (SOT) 5-pin package | 4 |

## CAD (KiCad official)

- Symbol: `TLV70025QDDCRQ1`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tlv70025qddcrq1-etched.step` / `tlv70025qddcrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv70025qddcrq1.step` / `tlv70025qddcrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlv700xx-q1) (25 pp, sha256 `a43d239fcc5c80dc`, retrieved 2026-11-05, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlv70025qddcrq1-datasheet.pdf)