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TLV62585DRLT

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Texas Instruments DC-DC Converters, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLV62585DRLT

Texas Instruments · DC-DC Converters · SOT-563

TLV62585DRLT from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin of the DRL (SOT563) package, which has a single combined ground in place of separate PGND and AGND.
2 SW passive Switch pin connected to the internal FET switches and inductor terminal; connect the output-filter inductor to this pin (DC range -0.3 V to VIN + 0.3 V).
3 VIN power_in Power supply voltage pin, recommended operating range 2.5 V to 5.5 V.
4 EN input Device enable logic input where high enables the device and low disables it into shutdown; do not leave floating.
5 FB input Feedback pin for the internal control loop; connect to an external feedback divider (absolute maximum -0.3 V to 3 V).
6 NC unconnected No connection pin on the DRL package; leave open or connect to the output or to AGND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-563
Category Power Supply Chip
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Feedback regulation voltage (0°C to 85°C) VFB 594 600 606 mV PWM mode, 2.5 V ≤ VIN ≤ 5.5 V, 0°C to 85°C 5
Feedback regulation voltage (-40°C to 125°C) VFB 588 600 612 mV PWM mode, 2.5 V ≤ VIN ≤ 5.5 V, -40°C to 125°C 5
Quiescent current into VIN IQ 35 µA No load, device not switching 5
Shutdown current into VIN ISD 0.7 2 µA EN = Low 5
Under voltage lock out threshold VUVLO 2.3 2.45 V VIN falling 5
High-level input voltage VIH 1.2 V VIN = 2.5 V to 5.5 V 5
Low-level input voltage VIL 0.4 V VIN = 2.5 V to 5.5 V 5
PG low-level output voltage VPG,OL 0.4 V Isink = 1 mA 5
High-side FET switch current limit ILIM 4 4.6 A 5
Under voltage lock out hysteresis 150 mV 5
Thermal shutdown threshold TJSD 150 °C TJ rising 5
Thermal shutdown hysteresis 20 °C 5
Soft start time tSS 900 µs Time from EN high to 95% of VOUT nominal 5
Power good threshold rising VPG 95 % VOUT rising, referenced to VOUT nominal 5
Power good threshold falling VPG 90 % VOUT falling, referenced to VOUT nominal 5
PG input leakage current IPG,LKG 0.01 µA VPG = 5.0 V 5
Power good delay tPG,DLY 40 µs VFB falling 5
Feedback input leakage current IFB,LKG 0.01 µA VFB = 0.6 V 5
Output discharge FET on-resistance RDIS 10 Ω EN = Low, VOUT = 1.8 V 5
High-side FET on-resistance RDS(on) 56 mΩ 5
Low-side FET on-resistance RDS(on) 32 mΩ 5
PWM switching frequency fSW 1.5 MHz VOUT = 1.8V, IOUT = 1 A 5
Voltage at VIN, EN, PG pins -0.3 6 V 4
Voltage at FB pin -0.3 3 V 4
Voltage at SW pin (DC) -0.3 6 V VIN + 0.3 max 4
Voltage at SW pin (AC) -3 9 V AC, less than 10ns, while switching 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
Input voltage range VIN 2.5 5.5 V 4
Output voltage range VOUT 0.6 5.5 V max is VIN 4
Sink current at PG pin ISINK_PG 1 mA 4
Output current IOUT 0 3 A 4
Operating junction temperature TJ -40 125 °C 4
Junction-to-ambient thermal resistance RθJA 132.7 °C/W DRL [SOT] 4
Junction-to-case (top) thermal resistance RθJC(top) 43.8 °C/W DRL [SOT] 4
Junction-to-board thermal resistance RθJB 27.3 °C/W DRL [SOT] 4
Junction-to-top characterization parameter ψJT 1.2 °C/W DRL [SOT] 4
Junction-to-board characterization parameter ψJB 26.6 °C/W DRL [SOT] 4
ESD HBM V(ESD) -2000 2000 V Human body model, per ANSI/ESDA/JEDEC JS-001 4
ESD CDM V(ESD) -500 500 V Charged device model, per JEDEC JESD22-C101 4

CAD (KiCad official)

  • Symbol: TLV62585DRLT
  • Footprint: Package_TO_SOT_SMD:SOT-563
  • 3D model: SOT-563 (KiCad packages3D, STEP)
  • 3D model files: tlv62585drlt-etched.step / tlv62585drlt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv62585drlt.step / tlv62585drlt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 5197526f61151dbc, retrieved 2026-10-27, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF