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TLV62568ADRLR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLV62568ADRLR
Texas Instruments · DC-DC Converters · SOT-563
TLV62568ADRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback pin for the internal control loop, connected to an external feedback divider (absolute maximum -0.3 V to 3 V). |
| 2 | GND | power_in | Ground pin. |
| 3 | VIN | power_in | Power supply voltage input, operating range 2.5 V to 5.5 V (absolute maximum 6 V). |
| 4 | SW | output | Switch pin connected to the internal FET switches and the output inductor terminal (DC -0.3 V to VIN + 0.3 V). |
| 5 | EN | input | Device enable logic input with high level above 1.2 V enabling and low level below 0.4 V shutting down the device; do not leave floating. |
| 6 | NC | unconnected | No connection pin on the non-power-good variant; it can be connected to the output or ground for better thermal performance, or left floating. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | Power Management ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage VIN, EN, PG | -0.3 | 6 | V | 3 | |||
| SW voltage (DC) | -0.3 | V | max printed as VIN + 0.3 | 3 | |||
| SW voltage (AC, less than 10ns) | -3 | 9 | V | While switching | 3 | ||
| FB voltage | -0.3 | 3 | V | 3 | |||
| Junction temperature | TJ | -40 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Input voltage | VIN | 2.5 | 5.5 | V | 4 | ||
| Output voltage | VOUT | 0.6 | V | max printed as VIN | 4 | ||
| Output current | IOUT | 0 | 2 | A | 4 | ||
| Junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Shutdown current into VIN pin | ISD | 0.01 | 2 | µA | EN = 0 V | 4 | |
| Under voltage lock out | VUVLO | 2.3 | 2.45 | V | VIN falling | 4 | |
| Under voltage lock out hysteresis | VUVLO | 100 | mV | 4 | |||
| Thermal shutdown, rising | TJSD | 150 | °C | TJ rising | 4 | ||
| Thermal shutdown, falling | TJSD | 130 | °C | TJ falling | 4 | ||
| High-level input voltage at EN pin | VIH | 1.2 | V | 2.5 ≤ VIN ≤ 5.5 | 4 | ||
| Low-level input voltage at EN pin | VIL | 0.4 | V | 2.5 ≤ VIN ≤ 5.5 | 4 | ||
| Soft startup time | tSS | 0.9 | ms | From EN high to 95% of VOUT nominal | 4 | ||
| Feedback regulation voltage | VFB | 0.588 | 0.6 | 0.612 | V | 5 | |
| Input leakage current into FB pin | IFB | 10 | nA | VFB = 0.6 V | 5 | ||
| High-side FET on resistance | RDS(on) | 100 | mΩ | 5 | |||
| Low-side FET on resistance | RDS(on) | 60 | mΩ | 5 | |||
| High-side FET current limit | ILIM | 2 | A | TLV62568A, TLV62568AP | 5 | ||
| Switching frequency | fSW | 1.5 | MHz | 5 | |||
| Junction-to-ambient thermal resistance (JEDEC) | RθJA | 142.8 | °C/W | JEDEC (DRL), 6 pins | 4 | ||
| Junction-to-ambient thermal resistance (EVM) | RθJA | 124.8 | °C/W | EVM (DRL), 6 pins | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 51.1 | °C/W | JEDEC (DRL) | 4 | ||
| Junction-to-board thermal resistance | RθJB | 28.9 | °C/W | JEDEC (DRL) | 4 | ||
| Junction-to-top characterization parameter (JEDEC) | ΨJT | 1.4 | °C/W | JEDEC (DRL) | 4 | ||
| Junction-to-top characterization parameter (EVM) | ΨJT | 1.6 | °C/W | EVM (DRL) | 4 | ||
| Junction-to-board characterization parameter (JEDEC) | ΨJB | 28.7 | °C/W | JEDEC (DRL) | 4 | ||
| Junction-to-board characterization parameter (EVM) | ΨJB | 23.1 | °C/W | EVM (DRL) | 4 |
CAD (KiCad official)
- Symbol:
TLV62568ADRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
tlv62568adrlr-etched.step/tlv62568adrlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv62568adrlr.step/tlv62568adrlr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
65a66c8ff8c7000f, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).