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TLV62565DBVR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs tlv62565dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tlv62565dbvr: viewers · Ray 1mo ago
package.json tlv62565dbvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json tlv62565dbvr: specified limits as data (metadata.characteristics, 36 rows from the datasheet) · Ray 26d ago
README.md tlv62565dbvr: specified limits as data (metadata.characteristics, 36 rows from the datasheet) · Ray 26d ago
tlv62565dbvr-etched.fit.json tlv62565dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tlv62565dbvr-etched.glb tlv62565dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tlv62565dbvr-etched.step tlv62565dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tlv62565dbvr.glb Publish 0.1.0 · Ray 1mo ago
tlv62565dbvr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tlv62565dbvr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tlv62565dbvr.lbr Publish 0.1.0 · Ray 1mo ago
tlv62565dbvr.step Publish 0.1.0 · Ray 1mo ago

TLV62565DBVR

Texas Instruments · DC-DC Converters · SOT-23-5

TLV62565DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Device enable logic input; logic HIGH enables device, logic LOW disables device and enters shutdown; do not leave floating.
2 GND power_in Ground pin.
3 SW passive Switch pin connected to internal MOSFET switches and inductor terminal; voltage range -0.3 V to VIN+0.3 V.
4 VIN power_in Power supply voltage input; recommended operating range 2.7 V to 5.5 V.
5 FB input Feedback pin for internal control loop connected to external feedback divider; feedback regulation voltage 0.588 V to 0.612 V nominal 0.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN 2.7 5.5 V 5
Quiescent current into VIN pin IQ 50 uA IOUT = 0 mA, Not switching 5
Under voltage lock out (falling threshold) VUVLO 2.2 2.3 V VIN falling 5
Under voltage lock out hysteresis VUVLO 200 mV 5
Thermal shutdown TJSD 150 °C Junction temperature rising 5
Thermal shutdown hysteresis TJSD 20 °C Junction temperature falling below TJSD 5
High-level input voltage (TLV62565 EN) VIH 1.2 V 2.7 V ≤ VIN ≤ 5.5 V 5
Low-level input voltage (TLV62565 EN) VIL 0.4 V 2.7 V ≤ VIN ≤ 5.5 V 5
Shutdown current into VIN pin ISD 0.1 1 µA EN = LOW 5
EN leakage current IEN,LKG 0.01 0.16 µA 5
Feedback regulation voltage VFB 0.588 0.6 0.612 V PWM operation, TA = -40°C to 85°C 5
Feedback regulation voltage at 85°C VFB 0.594 0.6 0.606 V PWM operation, TA = 85°C 5
PFM comparator threshold 0.9 % 5
Feedback input bias current IFB 10 100 nA VFB = 0.6 V 5
High-side FET on resistance RDS(on) 173 mΩ ISW = 500 mA, VIN = 3.6 V 5
Low-side FET on resistance RDS(on) 105 mΩ ISW = 500 mA, VIN = 3.6 V 5
Low-side FET valley current limit ILIM,LS 1.5 1.7 A 5
High-side FET peak current limit ILIM,HS 1.8 2 A 5
Switching frequency fSW 1.5 MHz 5
Maximum duty cycle DMAX 95 % 1
Minimum off time tOFF,MIN 40 ns 5
Input voltage (recommended) VIN 2.7 5.5 V 4
Operating ambient temperature TA -40 85 °C 4
Voltage on VIN, EN, PG VIN, EN, PG -0.3 7 V All voltage values with respect to network ground 4
Voltage on SW SW -0.3 V Maximum printed as VIN+0.3 V 4
Voltage on FB FB -0.3 3.6 V 4
Sink current on PG IPG 660 µA 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD human-body model V(ESD) -2000 2000 V HBM per ANSI/ESDA/JEDEC JS-001 4
ESD charged-device model V(ESD) -500 500 V CDM per JEDEC JESD22-C101 4
Junction-to-ambient thermal resistance (DBV) RθJA 208.3 °C/W 4
Junction-to-case (top) thermal resistance (DBV) RθJC(top) 73.7 °C/W 4
Junction-to-board thermal resistance (DBV) RθJB 36.1 °C/W 4
Junction-to-top characterization parameter (DBV) ψJT 2.3 °C/W 4
Junction-to-board characterization parameter (DBV) ψJB 35.3 °C/W 4

CAD (KiCad official)

  • Symbol: TLV62565DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv62565dbvr-etched.step / tlv62565dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv62565dbvr.step / tlv62565dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 acec9293334c09b5, retrieved 2026-09-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF