component
TLV62150RGTR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLV62150RGTR
Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)
TLV62150RGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor. |
| 2 | SW | output | Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor. |
| 3 | SW | output | Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor. |
| 4 | PG | output | Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain (requires pull-up resistor). |
| 5 | FB | input | Voltage feedback. Connect resistive voltage divider to this pin. |
| 6 | AGND | power_in | Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane. |
| 7 | FSW | input | Switching Frequency Select (Low ≈ 2.5 MHz, High ≈ 1.25 MHz for typical operation). |
| 8 | DEF | input | Output Voltage Scaling (Low = nominal, High = nominal + 5%). |
| 9 | SS/TR | input | Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise time. It can be used for tracking and sequencing. |
| 10 | AVIN | power_in | Supply voltage for control circuitry. Connect to same source as PVIN. |
| 11 | PVIN | power_in | Supply voltage for power stage. Connect to same source as AVIN. |
| 12 | PVIN | power_in | Supply voltage for power stage. Connect to same source as AVIN. |
| 13 | EN | input | Enable input (High = enabled, Low = disabled). |
| 14 | VOS | input | Output voltage sense pin and connection for the control loop circuitry. |
| 15 | PGND | power_in | Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane. |
| 16 | PGND | power_in | Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Pin voltage AVIN, PVIN | -0.3 | 20 | V | 5 | |||
| Pin voltage EN, SS/TR | -0.3 | V | 5 | ||||
| Pin voltage SW | -0.3 | V | 5 | ||||
| Pin voltage DEF, FSW, FB, PG, VOS | -0.3 | 7 | V | 5 | |||
| Power Good sink current | 10 | mA | PG | 5 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Electrostatic discharge, human body model (HBM) | VESD | -2000 | 2000 | V | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins | 5 | |
| Electrostatic discharge, charged device model (CDM) | VESD | -500 | 500 | V | Charged device model (CDM), per JEDEC specification JESD22-C101, all pins | 5 | |
| Supply Voltage | 4 | 17 | V | 5 | |||
| Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| VIN Input Voltage Range | VIN | 4 | 17 | V | 6 | ||
| IQ Operating Quiescent Current | IQ | 19 | 27 | μA | EN=High, IOUT=0 mA, device not switching | 6 | |
| ISD Shutdown Current | ISD | 1.5 | 4 | μA | EN=Low | 6 | |
| VUVLO Undervoltage Lockout Threshold | VUVLO | 2.6 | 2.7 | 2.8 | V | Falling Input Voltage (PWM mode operation) | 6 |
| Input Leakage Current (EN, DEF, FSW) | ILKG | 0.01 | 1 | μA | EN=VIN or GND; DEF, FSW=VOUT or GND | 6 | |
| Power Good Threshold Voltage, Rising (%VOUT) | VTH_PG | 92 | 95 | 98 | % | 6 | |
| Power Good Threshold Voltage, Falling (%VOUT) | VTH_PG | 87 | 90 | 94 | % | 6 | |
| Power Good Output Low | VOL_PG | 0.07 | 0.3 | V | IPG=-2 mA | 6 | |
| Input Leakage Current (PG) | ILKG_PG | 1 | 400 | nA | VPG=1.8 V | 6 | |
| SS/TR Pin Source Current | ISS/TR | 2.3 | 2.5 | 2.7 | μA | 6 | |
| Input Leakage Current (FB) | ILKG_FB | 1 | 100 | nA | VFB=0.8 V | 6 | |
| Output Voltage Range | VOUT | 0.9 | 5 | V | VIN ≥ VOUT | 6 | |
| Initial Output Voltage Accuracy | 780 | 800 | 820 | mV | PWM mode operation, VIN ≥ VOUT +1 V | 6 | |
| Junction-to-ambient thermal resistance | RθJA | 45 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 53.6 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 17.4 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 1.1 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 17.4 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 4.5 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TLV62150RGTR - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tlv62150rgtr-etched.step/tlv62150rgtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv62150rgtr.step/tlv62150rgtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
ad0a9b1330b05a75, retrieved 2026-09-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).