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Contents

README

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TLV62130RGTT

Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)

TLV62130RGTT from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW output Switch node connected to internal MOSFET switches; connect inductor between this node and output capacitor.
2 SW output Switch node connected to internal MOSFET switches; connect inductor between this node and output capacitor.
3 SW output Switch node connected to internal MOSFET switches; connect inductor between this node and output capacitor.
4 PG output Open-drain power good output; high = VOUT ready, low = VOUT below nominal regulation; maximum sink current 2 mA at 0.3 V output low.
5 FB input Voltage feedback input for output regulation via resistive divider; regulated to 0.8 V nominal setpoint; maximum leakage 100 nA.
6 AGND power_in Analog ground reference; must be connected directly to exposed thermal pad and common ground plane.
7 FSW input Switching frequency select input; low ≈ 2.5 MHz, high ≈ 1.25 MHz typical operation; logic thresholds 0.3 V low, 0.9 V high.
8 DEF input Output voltage scaling input; low = nominal voltage, high = nominal + 5%; logic thresholds 0.3 V low, 0.9 V high; internal pull-down 400 kΩ.
9 SS/TR input Soft-start and tracking pin; external capacitor controls output voltage ramp time with 2.5 µA source current.
10 AVIN power_in Analog supply voltage input for control circuitry; connect to same source as PVIN; operating range 3 V to 17 V.
11 PVIN power_in Power supply voltage input for power stage; connect to same source as AVIN; operating range 3 V to 17 V.
12 PVIN power_in Power supply voltage input for power stage; connect to same source as AVIN; operating range 3 V to 17 V.
13 EN input Enable control input; high = enabled, low = disabled; logic thresholds 0.3 V low, 0.9 V high; internal pull-down 400 kΩ.
14 VOS input Output voltage sense input for control loop feedback; connect to VOUT at output capacitor with short, isolated trace.
15 PGND power_in Power ground reference; must be connected directly to exposed thermal pad and common ground plane.
16 PGND power_in Power ground reference; must be connected directly to exposed thermal pad and common ground plane.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

CAD (KiCad official)

  • Symbol: TLV62130RGTT
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tlv62130rgtt-etched.step / tlv62130rgtt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv62130rgtt.step / tlv62130rgtt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 0065382c4a9061fe, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF