component
TLV62130ARGTT
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTLV62130ARGTT
Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)
TLV62130ARGTT from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switch node connected to the internal MOSFET switches; connect the inductor between SW and the output capacitor. |
| 2 | SW | output | Switch node connected to the internal MOSFET switches; connect the inductor between SW and the output capacitor. |
| 3 | SW | output | Switch node connected to the internal MOSFET switches; connect the inductor between SW and the output capacitor. |
| 4 | PG | output | Open-drain output power good (High = VOUT ready, Low = VOUT below nominal regulation); requires a pull-up resistor. |
| 5 | FB | input | Voltage feedback input; connect a resistive voltage divider to this pin. |
| 6 | AGND | power_in | Analog ground; must be connected directly to the exposed thermal pad and common ground plane. |
| 7 | FSW | input | Switching frequency select (Low ≈ 2.5 MHz, High ≈ 1.25 MHz for typical operation); connect FSW to VOUT or PG for the High setting; internal pull-down keeps it low if floating. |
| 8 | DEF | input | Output voltage scaling (Low = nominal, High = nominal + 5%); internal pull-down keeps it low if floating. |
| 9 | SS/TR | input | Soft-start/tracking pin; an external capacitor sets the internal voltage reference rise time and it can be used for tracking and sequencing. |
| 10 | AVIN | power_in | Supply voltage for control circuitry (3 V to 17 V recommended); connect to the same source as PVIN. |
| 11 | PVIN | power_in | Supply voltage for the power stage (3 V to 17 V recommended); connect to the same source as AVIN. |
| 12 | PVIN | power_in | Supply voltage for the power stage (3 V to 17 V recommended); connect to the same source as AVIN. |
| 13 | EN | input | Enable input (High = enabled, Low = disabled); internal pull-down keeps it low if floating. |
| 14 | VOS | input | Output voltage sense pin and connection for the control loop circuitry. |
| 15 | PGND | power_in | Power ground; must be connected directly to the exposed thermal pad and common ground plane. |
| 16 | PGND | power_in | Power ground; must be connected directly to the exposed thermal pad and common ground plane. |
| 17 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16-EP(3x3) |
| Category | Power Supply Chip |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 3 | 17 | V | 6 | ||
| Operating Quiescent Current | IQ | 19 | 27 | μA | EN=High, IOUT = 0 mA, device not switching | 6 | |
| Shutdown Current | ISD | 1.5 | 4 | μA | EN=Low | 6 | |
| Undervoltage Lockout Threshold | VUVLO | 2.6 | 2.7 | 2.8 | V | Falling Input Voltage (PWM mode operation) | 6 |
| UVLO Hysteresis | 200 | mV | 6 | ||||
| Thermal Shutdown Temperature | TSD | 160 | °C | 6 | |||
| Thermal Shutdown Hysteresis | 20 | °C | 6 | ||||
| High Level Input Threshold Voltage (EN, DEF, FSW) | VH | 0.9 | V | 6 | |||
| Low Level Input Threshold Voltage (EN, DEF, FSW) | VL | 0.3 | V | 6 | |||
| Input Leakage Current (EN, DEF, FSW) | ILKG | 0.01 | 1 | μA | EN = VIN or GND; DEF, FSW = VOUT or GND | 6 | |
| Power Good Threshold Rising | VTH_PG | 92 | 95 | 98 | %VOUT | Rising (%VOUT) | 6 |
| Power Good Threshold Falling | VTH_PG | 87 | 90 | 94 | %VOUT | Falling (%VOUT) | 6 |
| Power Good Output Low | VOL_PG | 0.07 | 0.3 | V | IPG = -2 mA | 6 | |
| Input Leakage Current (PG) | ILKG_PG | 1 | 400 | nA | VPG = 1.8 V | 6 | |
| SS/TR Pin Source Current | ISS/TR | 2.3 | 2.5 | 2.7 | μA | 6 | |
| High-Side MOSFET ON-Resistance | RDS(ON) | 90 | mΩ | VIN ≥ 6 V | 6 | ||
| Low-Side MOSFET ON-Resistance | RDS(ON) | 40 | mΩ | VIN ≥ 6 V | 6 | ||
| High-Side MOSFET Forward Current Limit | ILIMF | 3.6 | 4.2 | A | VIN = 12 V, TA = 25°C | 6 | |
| Input Leakage Current (FB) | ILKG_FB | 1 | 100 | nA | VFB = 0.8 V | 6 | |
| Output Voltage Range | VOUT | 0.9 | 5.5 | V | VIN ≥ VOUT | 6 | |
| Initial Output Voltage Accuracy (FB voltage) | VFB | 780 | 800 | 820 | mV | PWM mode operation, VIN ≥ VOUT +1 V | 6 |
| Load Regulation | 0.05 | %/A | VIN = 12 V, VOUT = 3.3 V, PWM mode operation | 6 | |||
| Line Regulation | 0.02 | %/V | 4 V ≤ VIN ≤ 17 V, VOUT = 3.3 V, IOUT = 1 A, PWM mode operation | 6 | |||
| Pin voltage AVIN, PVIN | -0.3 | 20 | V | 5 | |||
| Pin voltage EN, SS/TR | -0.3 | V | max VIN+0.3 | 5 | |||
| Pin voltage SW (DC) | -0.3 | V | max VIN+0.3 | 5 | |||
| Pin voltage SW (AC) | -2 | 24.5 | V | less than 10ns, while switching | 5 | ||
| Pin voltage DEF, FSW, FB, PG, VOS | -0.3 | 7 | V | 5 | |||
| Power Good sink current | 10 | mA | PG | 5 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| ESD HBM | VESD | -2000 | 2000 | V | HBM, all pins | 5 | |
| ESD CDM | VESD | -500 | 500 | V | CDM, all pins | 5 | |
| Supply Voltage | 3 | 17 | V | 5 | |||
| Operating free air temperature | TA | -40 | 85 | °C | 5 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 45 | °C/W | RGT [VQFN] 16 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 53.6 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 17.4 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 1.1 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 17.4 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 4.5 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TLV62130ARGTT - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tlv62130argtt-etched.step/tlv62130argtt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv62130argtt.step/tlv62130argtt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
1c43801408ca5f90, retrieved 2026-10-27, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).