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TLV62130ARGTR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, VQFN-16-EP(3x3). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs tlv62130argtr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers tlv62130argtr: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md tlv62130argtr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 15d ago
tlv62130argtr-etched.fit.json tlv62130argtr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tlv62130argtr-etched.glb tlv62130argtr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tlv62130argtr-etched.step tlv62130argtr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tlv62130argtr.glb Publish 0.1.0 · Ray 1mo ago
tlv62130argtr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tlv62130argtr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tlv62130argtr.lbr Publish 0.1.0 · Ray 1mo ago
tlv62130argtr.step Publish 0.1.0 · Ray 1mo ago

TLV62130ARGTR

Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)

TLV62130ARGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW output Switch node connected to the internal MOSFET switches. Connect the external power inductor between SW and the output capacitor. Pins 1, 2, and 3 are internally tied.
2 SW output Switch node connected to the internal MOSFET switches. Connect the external power inductor between SW and the output capacitor. Pins 1, 2, and 3 are internally tied.
3 SW output Switch node connected to the internal MOSFET switches. Connect the external power inductor between SW and the output capacitor. Pins 1, 2, and 3 are internally tied.
4 PG output Power Good output (open-drain). High impedance when VOUT is within regulation, low when VOUT is below nominal regulation. Requires an external pull-up resistor; sinks up to 10 mA.
5 FB input Voltage feedback input. Connect a resistive voltage divider from VOUT to this pin to program the adjustable output voltage (0.9 V to 5.5 V).
6 AGND power_in Analog ground. Must be connected directly to the exposed thermal pad and the common ground plane.
7 FSW input Switching frequency select. Low approx 2.5 MHz, High approx 1.25 MHz for typical operation. Internal pull-down keeps logic low if the pin is floating; connect FSW to VOUT or PG for high setting.
8 DEF input Output voltage scaling select. Low = nominal VOUT, High = nominal + 5%. Internal pull-down resistor keeps the logic level low when the pin is floating.
9 SS/TR input Soft-Start / Tracking pin. An external capacitor sets the internal voltage-reference rise time; can also be used as a tracking and sequencing input.
10 AVIN power_in Supply voltage for the control circuitry (3 V to 17 V). Connect to the same source as PVIN.
11 PVIN power_in Supply voltage for the power stage (3 V to 17 V). Connect to the same source as AVIN. Pins 11 and 12 are internally tied.
12 PVIN power_in Supply voltage for the power stage (3 V to 17 V). Connect to the same source as AVIN. Pins 11 and 12 are internally tied.
13 EN input Enable input. High = device enabled, Low = device disabled/shutdown (< 2 uA). Absolute maximum -0.3 V to VIN+0.3 V.
14 VOS input Output voltage sense pin and connection point for the control loop circuitry. Route this pin directly to the output node.
15 PGND power_in Power ground. Must be connected directly to the exposed thermal pad and the common ground plane. Pins 15 and 16 are internally tied.
16 PGND power_in Power ground. Must be connected directly to the exposed thermal pad and the common ground plane. Pins 15 and 16 are internally tied.
17 EP power_in Exposed thermal pad. Must be connected to AGND (pin 6), PGND (pins 15, 16) and the common ground plane, and soldered to the PCB to achieve appropriate power dissipation and mechanical reliability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category PMIC
Pins 17

Ordering variants

Same part, different packaging or reel option.

  • TLV62130ARGTR
  • TLV62130ARGTRRGTT

CAD (KiCad official)

  • Symbol: TLV62130ARGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tlv62130argtr-etched.step / tlv62130argtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv62130argtr.step / tlv62130argtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 62f8ffdeab73ad95, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF