# TLV62084DSGR

**Texas Instruments** · DC-DC Converters · WSON-8-EP(2x2)

TLV62084DSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Device enable logic input; logic HIGH enables the device, logic LOW disables it into shutdown, and it must not be left floating. |
| 2 | GND | power_in | Power and signal ground. |
| 3 | GND | power_in | Power and signal ground. |
| 4 | FB | input | Feedback terminal for the internal control loop; connect to the external feedback divider to program the output voltage. |
| 5 | VOS | input | Output voltage sense terminal for the internal control loop; must be connected to the output. |
| 6 | PG | output | Open-drain power good output that is pulled low when the output voltage is below regulation limits; it can be left floating if unused and sinks typically up to 0.5 mA. |
| 7 | SW | power_out | Switch terminal connected to the internal MOSFET switches and the inductor; connect the output filter inductor here. |
| 8 | VIN | power_in | Power supply voltage input. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-8-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range, TLV62084 | VIN | 2.7 |  | 6 | V |  | 6 |
| Operating junction temperature range | TJ | -40 |  | 125 | °C |  | 5 |
| Input voltage range (absolute max, VIN, PG, VOS) | VIN, PG, VOS | -0.3 |  | 7 | V |  | 5 |
| Voltage range SW | SW | -0.3 |  |  | V | Referenced to VIN + 0.3 V | 5 |
| Voltage range SW (AC) | SW | -3 |  | 10 | V | AC, less than 10 ns, while switching | 5 |
| Voltage range FB | FB | -0.3 |  | 3.6 | V |  | 5 |
| Voltage range EN | EN | -0.3 |  |  | V | Referenced to VIN + 0.3 V | 5 |
| Power Good sink current | PG |  |  | 1 | mA |  | 5 |
| Operating junction temperature range (absolute max) | TJ | -40 |  | 150 | °C |  | 5 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 5 |
| Quiescent current into VIN | IQ |  |  | 30 | µA | IOUT = 0 mA, device not switching | 6 |
| Shutdown current into VIN | ISD |  |  | 1 | µA | EN = LOW | 6 |
| Under voltage lock out | VUVLO | 1.8 |  | 2 | V | Input voltage falling | 6 |
| Under voltage lock out hysteresis |  |  |  | 120 | mV | Rising above VUVLO | 6 |
| Thermal shutdown | TJSD |  |  | 150 | °C | Temperature rising | 6 |
| Thermal shutdown hysteresis |  |  |  | 20 | °C | Temperature falling below TJSD | 6 |
| High level input voltage (EN) | VIH |  |  | 1 | V | 2.5 V ≤ VIN ≤ 6 V | 6 |
| Low level input voltage (EN) | VIL |  |  | 0.4 | V | 2.5 V ≤ VIN ≤ 6 V | 6 |
| Input leakage current (EN) | ILKG |  | 0.01 | 0.5 | µA |  | 6 |
| Power good threshold | VPG | -15 | -10 | -5 | % | VOUT falling referenced to VOUT nominal | 6 |
| Power good hysteresis |  |  |  | 5 | % |  | 6 |
| Low level voltage (PG) | VOL |  |  | 0.3 | V | Isink = 500 µA | 6 |
| PG leakage current | IPG,LKG |  | 0.01 | 0.1 | µA | VPG = 5.0 V | 6 |
| Output voltage range | VOUT | 0.5 |  | 4 | V |  | 6 |
| Feedback regulation voltage | VFB | 0.438 | 0.45 | 0.462 | V | VIN ≥ 2.5 V and VIN ≥ VOUT + 1 V | 6 |
| Feedback input bias current | IFB |  | 10 | 100 | nA | VFB = 0.45 V | 6 |
| Output discharge resistor | RDIS |  | 1 |  | kΩ | EN = LOW, VOUT = 1.8 V | 6 |
| High side FET on-resistance | RDS(on) |  | 120 |  | mΩ | ISW = 500 mA | 6 |
| Low side FET on-resistance | RDS(on) |  | 90 |  | mΩ | ISW = 500 mA | 6 |
| High side FET switch current-limit, TLV62084, TLV62084A | ILIM | 2.3 | 2.8 | 4 | A | Rising inductor current | 6 |
| Junction-to-ambient thermal resistance | θJA |  | 59.7 |  | °C/W |  | 5 |
| Junction-to-case (top) thermal resistance | θJCtop |  | 70.1 |  | °C/W |  | 5 |
| Junction-to-board thermal resistance | θJB |  | 30.9 |  | °C/W |  | 5 |
| Junction-to-top characterization parameter | ψJT |  | 1.4 |  | °C/W |  | 5 |
| Junction-to-board characterization parameter | ψJB |  | 31.5 |  | °C/W |  | 5 |
| Junction-to-case (bottom) thermal resistance | θJCbot |  | 8.6 |  | °C/W |  | 5 |

## CAD (KiCad official)

- Symbol: `TLV62084DSGR`
- Footprint: `Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm`
- 3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `tlv62084dsgr-etched.step` / `tlv62084dsgr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv62084dsgr.step` / `tlv62084dsgr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tlv62084.pdf) (30 pp, sha256 `379c8612154eb2b4`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlv62084dsgr-datasheet.pdf)