component
TLV5637CDR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 14d ago |
| viewers | 14d ago |
| package.json | 14d ago |
| page.json | 14d ago |
| README.md | 14d ago |
| tlv5637cdr-etched.glb | 14d ago |
| tlv5637cdr-etched.step | 14d ago |
| tlv5637cdr-hero.glb | 14d ago |
| tlv5637cdr-hero.overlay.json | 14d ago |
| tlv5637cdr.glb | 14d ago |
| tlv5637cdr.kicad_mod | 14d ago |
| tlv5637cdr.kicad_sym | 14d ago |
| tlv5637cdr.lbr | 14d ago |
| tlv5637cdr.step | 14d ago |
TLV5637CDR
Texas Instruments · Digital To Analog Converters (DAC) · SOIC-8
TLV5637CDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIN | input | Digital serial data input; data is shifted in MSB first on the falling SCLK edges, with 10 ns setup and 5 ns hold before and after the falling edge. |
| 2 | SCLK | input | Digital serial clock input; the maximum serial clock frequency is 20 MHz. |
| 3 | CS | input | Chip select, digital input active low, used to enable and disable the serial inputs. |
| 4 | OUTA | output | DAC A analog voltage output, which swings from 0 V to VDD - 0.4 V into a 10 kΩ load (minimum load 2 kΩ, maximum load capacitance 100 pF). |
| 5 | AGND | power_in | Ground reference pin for the device. |
| 6 | REF | bidirectional | Analog reference voltage input/output; if an external reference is used the internal reference output buffer must be disabled, and a reference at or above (VDD - 0.4 V)/2 causes clipping of the transfer function. |
| 7 | OUTB | output | DAC B analog voltage output, which swings from 0 V to VDD - 0.4 V into a 10 kΩ load (minimum load 2 kΩ, maximum load capacitance 100 pF). |
| 8 | VDD | power_in | Positive power supply, specified at 4.5 V to 5.5 V for VDD = 5 V operation and 2.7 V to 3.3 V for VDD = 3 V operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Data Acquisition |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TLV5637CDR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tlv5637cdr-etched.step/tlv5637cdr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv5637cdr.step/tlv5637cdr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
b85db5daee010238, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).