component
TLV5632IPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "TLV5632IPWR",
"brief": "Texas Instruments Digital To Analog Converters (DAC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
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"component": {
"mpn": "TLV5632IPWR",
"manufacturer": "Texas Instruments",
"package": "TSSOP-20",
"pin_count": 20,
"category": "Data Acquisition",
"subcategory": "Digital To Analog Converters (DAC)",
"datasheet": "https://www.ti.com/cn/lit/gpn/tlv5630",
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"lcsc": "C2679759",
"digikey": "TLV5632IPWR-ND",
"mouser": "595-TLV5632IPWR"
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"pins": [
{
"number": "1",
"name": "DGND",
"type": "power_in",
"description": "Digital ground for the digital interface circuitry."
},
{
"number": "2",
"name": "DIN",
"type": "input",
"description": "Digital serial data input; the 16-bit word (4 control and 12 data bits) is shifted in MSB first on the falling edges of SCLK after FS goes low."
},
{
"number": "3",
"name": "SCLK",
"type": "input",
"description": "Serial clock input, with a maximum serial clock frequency of 30 MHz."
},
{
"number": "4",
"name": "FS",
"type": "input",
"description": "Frame sync input; in µC mode FS must stay low until all 16 data bits are transferred and the DAC updates on its rising edge, while in DSP mode FS must stay low for at least 20 ns."
},
{
"number": "5",
"name": "PRE",
"type": "input",
"description": "Preset input; when driven low and LDAC is asserted, all DAC outputs go to the value stored in the preset register, and it is asynchronous to the clock."
},
{
"number": "6",
"name": "OUTE",
"type": "output",
"description": "DAC E buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load."
},
{
"number": "7",
"name": "OUTF",
"type": "output",
"description": "DAC F buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load."
},
{
"number": "8",
"name": "OUTG",
"type": "output",
"description": "DAC G buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load."
},
{
"number": "9",
"name": "OUTH",
"type": "output",
"description": "DAC H buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load."
},
{
"number": "10",
"name": "AGND",
"type": "power_in",
"description": "Analog ground for the DAC and output circuitry."
},
{
"number": "11",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation; AVDD must power up before DVDD for correct power-on reset."
},
{
"number": "12",
"name": "OUTA",
"type": "output",
"description": "DAC A buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load."
},
{
"number": "13",
"name": "OUTB",
"type": "output",
"description": "DAC B buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load."
},
{
"number": "14",
"name": "OUTC",
"type": "output",
"description": "DAC C buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load."
},
{
"number": "15",
"name": "OUTD",
"type": "output",
"description": "DAC D buffered voltage output, specified 0 V to AVDD − 0.4 V at RL = 10 kΩ and able to drive 2 kΩ with 100 pF load."
},
{
"number": "16",
"name": "REF",
"type": "bidirectional",
"description": "Voltage reference input/output; accepts an external reference from 0 V to AVDD, or outputs an internal 1.024 V or 2.048 V reference that needs a 1 µF to 10 µF capacitor in parallel with 100 pF when used."
},
{
"number": "17",
"name": "MODE",
"type": "input",
"description": "DSP/µC mode select pin: high selects µC mode, and not connected (NC) selects DSP mode."
},
{
"number": "18",
"name": "LDAC",
"type": "input",
"description": "Load DAC; DAC outputs are updated only while LDAC is low, and it is an asynchronous input with a minimum low pulse width of 10 ns."
},
{
"number": "19",
"name": "DOUT",
"type": "output",
"description": "Digital serial data output that reproduces the DIN data with a 16-clock-cycle delay when DOUT is enabled, for daisy-chaining."
},
{
"number": "20",
"name": "DVDD",
"type": "power_in",
"description": "Digital power supply, using the same 4.5 V to 5.5 V or 2.7 V to 3.3 V ranges as AVDD and powering up after AVDD."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
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"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet gives the TSSOP (PW) outline and the grouped terminal table (OUTA-OUTH 12-15, 6-9); th; The MODE pin description is printed as 'NC = DSP mode' and the DSP/µC section says 'MODE = N.C. or 0"
],
"pages_sent": 25,
"cost_usd": 0.1025,
"at": "2026-10-11T14:51:28"
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"url": "https://www.ti.com/cn/lit/gpn/tlv5630",
"pages": 25,
"sha256": "fca921911e680eae",
"source_tier": "lcsc"
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"cad": "KiCad official (CC-BY-SA 4.0)",
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"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "TSSOP-20",
"Category": "Data Acquisition",
"Pins": "20"
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