TLV5624CDGKR

{
  "slug": "tlv5624cdgkr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Digital To Analog Converters (DACs), VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "adc-dac-data conversion",
    "tlv5624cdgkr",
    "factory-2.0.0",
    "extractor-text"
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  "dependencies": {},
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    "tlv5624cdgkr.step",
    "tlv5624cdgkr.lbr",
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    "docs/tlv5624cdgkr-datasheet.pdf",
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    "viewers/footprint.html",
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  "component": {
    "mpn": "TLV5624CDGKR",
    "manufacturer": "Texas Instruments",
    "package": "VSSOP-8",
    "pin_count": 8,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/tlv5624",
    "parts": {
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      "footprint": "tlv5624cdgkr.kicad_mod",
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      "lbr": "tlv5624cdgkr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2679601",
      "digikey": "TLV5624CDGKR-ND",
      "mouser": "595-TLV5624CDGKR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T16:15:26Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "TLV5624CDGKR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-TLV5624CDGKR",
        "status": "found"
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    },
    "pins": [
      {
        "number": "1",
        "name": "DIN",
        "type": "input",
        "description": "Digital serial data input; the 16-bit word carries 4 control bits and 8 data bits, shifted in MSB first on high-to-low SCLK transitions."
      },
      {
        "number": "2",
        "name": "SCLK",
        "type": "input",
        "description": "Digital serial clock input; the maximum serial clock frequency is 20 MHz."
      },
      {
        "number": "3",
        "name": "CS",
        "type": "input",
        "description": "Chip select, a digital input active low used to enable or disable the inputs; it can be tied low when only one device is on the serial bus."
      },
      {
        "number": "4",
        "name": "FS",
        "type": "input",
        "description": "Frame sync input; a falling edge starts the serial data shift, and the DAC updates after 16 bits are shifted in or on the FS rising edge."
      },
      {
        "number": "5",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground for the DAC; the datasheet recommends connecting it to the system analog ground plane."
      },
      {
        "number": "6",
        "name": "REF",
        "type": "bidirectional",
        "description": "Analog reference voltage input/output; a 0.1 µF bypass capacitor is required, plus 10 µF if the internal reference is used, and an external reference must stay within AGND to VDD−1.5 V."
      },
      {
        "number": "7",
        "name": "OUT",
        "type": "output",
        "description": "DAC A analog voltage output from a x2 gain rail-to-rail buffer, specified for load resistance of at least 2 kΩ and load capacitance up to 100 pF."
      },
      {
        "number": "8",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive power supply; the device is specified for single-supply operation from 2.7 V to 5.5 V."
      }
    ],
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        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 26,
        "cost_usd": 0.0937,
        "at": "2026-10-08T16:15:10"
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      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/tlv5624",
        "pages": 26,
        "sha256": "5ae4849781b211d0",
        "source_tier": "lcsc"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
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    },
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}