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TLV5608IPWR
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Texas Instruments Digital To Analog Converters (DAC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# TLV5608IPWR++**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-20++TLV5608IPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DGND | power_in | Digital ground for the device's digital logic. |+| 2 | DIN | input | Digital serial data input; after FS falls, data is shifted in MSB first on the falling edges of SCLK. |+| 3 | SCLK | input | Serial clock input, with a maximum serial clock frequency of 30 MHz. |+| 4 | FS | input | Frame-sync input whose falling edge starts a 16-bit write; in µC mode FS must stay low until all 16 bits are transferred. |+| 5 | PRE | input | Asynchronous preset input which, when driven low with LDAC asserted, sets all DAC outputs to the value stored in the preset register. |+| 6 | OUTE | output | DAC output E from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance. |+| 7 | OUTF | output | DAC output F from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance. |+| 8 | OUTG | output | DAC output G from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance. |+| 9 | OUTH | output | DAC output H from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance. |+| 10 | AGND | power_in | Analog ground for the DAC and output circuitry. |+| 11 | AVDD | power_in | Analog power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation; AVDD must come up before DVDD for correct power-on reset. |+| 12 | OUTA | output | DAC output A from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance. |+| 13 | OUTB | output | DAC output B from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance. |+| 14 | OUTC | output | DAC output C from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance. |+| 15 | OUTD | output | DAC output D from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance. |+| 16 | REF | input | Buffered, high-impedance voltage reference input with a 0 V to AVDD range and 100 kΩ input resistance. |+| 17 | MODE | input | DSP/µC mode select: high selects µC mode, not connected selects DSP mode. |+| 18 | LDAC | input | Asynchronous load-DAC input; DAC outputs are updated only while LDAC is low, with a minimum low duration of 10 ns. |+| 19 | DOUT | output | Serial data output that, when digital output is enabled, repeats DIN delayed by 16 clock cycles for daisy-chaining. |+| 20 | DVDD | power_in | Digital power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Data Acquisition |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `TLV5608IPWR`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `tlv5608ipwr-etched.step` / `tlv5608ipwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv5608ipwr.step` / `tlv5608ipwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlv5608) (25 pp, sha256 `5201b308030f0178`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlv5608ipwr-datasheet.pdf)
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after FS falls, data is shifted in MSB first on the falling edges of SCLK."+ },+ {+ "number": "3",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input, with a maximum serial clock frequency of 30 MHz."+ },+ {+ "number": "4",+ "name": "FS",+ "type": "input",+ "description": "Frame-sync input whose falling edge starts a 16-bit write; in µC mode FS must stay low until all 16 bits are transferred."+ },+ {+ "number": "5",+ "name": "PRE",+ "type": "input",+ "description": "Asynchronous preset input which, when driven low with LDAC asserted, sets all DAC outputs to the value stored in the preset register."+ },+ {+ "number": "6",+ "name": "OUTE",+ "type": "output",+ "description": "DAC output E from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance."+ },+ {+ "number": "7",+ "name": "OUTF",+ "type": "output",+ "description": "DAC output F from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance."+ },+ {+ "number": "8",+ "name": "OUTG",+ "type": "output",+ "description": "DAC output G from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance."+ },+ {+ "number": "9",+ "name": "OUTH",+ "type": "output",+ "description": "DAC output H from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance."+ },+ {+ "number": "10",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground for the DAC and output circuitry."+ },+ {+ "number": "11",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation; AVDD must come up before DVDD for correct power-on reset."+ },+ {+ "number": "12",+ "name": "OUTA",+ "type": "output",+ "description": "DAC output A from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance."+ },+ {+ "number": "13",+ "name": "OUTB",+ "type": "output",+ "description": "DAC output B from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance."+ },+ {+ "number": "14",+ "name": "OUTC",+ "type": "output",+ "description": "DAC output C from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance."+ },+ {+ "number": "15",+ "name": "OUTD",+ "type": "output",+ "description": "DAC output D from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance."+ },+ {+ "number": "16",+ "name": "REF",+ "type": "input",+ "description": "Buffered, high-impedance voltage reference input with a 0 V to AVDD range and 100 kΩ input resistance."+ },+ {+ "number": "17",+ "name": "MODE",+ "type": "input",+ "description": "DSP/µC mode select: high selects µC mode, not connected selects DSP mode."+ },+ {+ "number": "18",+ "name": "LDAC",+ "type": "input",+ "description": "Asynchronous load-DAC input; DAC outputs are updated only while LDAC is low, with a minimum low duration of 10 ns."+ },+ {+ "number": "19",+ "name": "DOUT",+ "type": "output",+ "description": "Serial data output that, when digital output is enabled, repeats DIN delayed by 16 clock cycles for daisy-chaining."+ },+ {+ "number": "20",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet gives one top-view and terminal table shared by the DW (SOIC) and PW (TSSOP) packages ; Supply pins AVDD and DVDD and grounds are typed power_in per KiCad convention; the datasheet labels "+ ],+ "pages_sent": 25,+ "cost_usd": 0.1124,+ "at": "2026-10-08T03:38:54"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlv5608",+ "pages": 25,+ "sha256": "5201b308030f0178",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlv5608ipwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlv5608ipwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "a57b2c8d6d21458620f1c7efb4797706068106e6366dc723c918ee1b2c401595",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}