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Contents

README

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TLV5608IPWR

Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-20

TLV5608IPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DGND power_in Digital ground for the device's digital logic.
2 DIN input Digital serial data input; after FS falls, data is shifted in MSB first on the falling edges of SCLK.
3 SCLK input Serial clock input, with a maximum serial clock frequency of 30 MHz.
4 FS input Frame-sync input whose falling edge starts a 16-bit write; in µC mode FS must stay low until all 16 bits are transferred.
5 PRE input Asynchronous preset input which, when driven low with LDAC asserted, sets all DAC outputs to the value stored in the preset register.
6 OUTE output DAC output E from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance.
7 OUTF output DAC output F from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance.
8 OUTG output DAC output G from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance.
9 OUTH output DAC output H from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance.
10 AGND power_in Analog ground for the DAC and output circuitry.
11 AVDD power_in Analog power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation; AVDD must come up before DVDD for correct power-on reset.
12 OUTA output DAC output A from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance.
13 OUTB output DAC output B from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance.
14 OUTC output DAC output C from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance.
15 OUTD output DAC output D from a buffered rail-to-rail amplifier that reliably drives a 2 kΩ load with 100 pF load capacitance.
16 REF input Buffered, high-impedance voltage reference input with a 0 V to AVDD range and 100 kΩ input resistance.
17 MODE input DSP/µC mode select: high selects µC mode, not connected selects DSP mode.
18 LDAC input Asynchronous load-DAC input; DAC outputs are updated only while LDAC is low, with a minimum low duration of 10 ns.
19 DOUT output Serial data output that, when digital output is enabled, repeats DIN delayed by 16 clock cycles for daisy-chaining.
20 DVDD power_in Digital power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Data Acquisition
Pins 20

CAD (KiCad official)

  • Symbol: TLV5608IPWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: tlv5608ipwr-etched.step / tlv5608ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv5608ipwr.step / tlv5608ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 5201b308030f0178, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF