component
TLV5608IDWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266
{
"slug": "tlv5608idwr",
"version": "0.1.0",
"type": "component",
"description": "Texas Instruments Digital To Analog Converters (DACs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"adc-dac-data conversion",
"tlv5608idwr",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"tlv5608idwr.kicad_sym",
"tlv5608idwr.kicad_mod",
"tlv5608idwr.glb",
"tlv5608idwr.step",
"tlv5608idwr.lbr",
"docs/hero.png",
"docs/tlv5608idwr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"tlv5608idwr-hero.glb",
"tlv5608idwr-hero.overlay.json"
],
"component": {
"mpn": "TLV5608IDWR",
"manufacturer": "Texas Instruments",
"package": "SOIC-20-300mil",
"pin_count": 20,
"category": "ADC/DAC/Data Conversion",
"subcategory": "Digital To Analog Converters (DACs)",
"datasheet": "https://www.ti.com/cn/lit/gpn/tlv5608",
"parts": {
"symbol": "tlv5608idwr.kicad_sym",
"footprint": "tlv5608idwr.kicad_mod",
"model_3d": "tlv5608idwr-hero.glb",
"model_3d_plain": "tlv5608idwr.glb",
"model_3d_step": "tlv5608idwr-etched.step",
"model_3d_step_plain": "tlv5608idwr.step",
"lbr": "tlv5608idwr.lbr"
},
"distributor_links": {
"lcsc": "C544359",
"digikey": "TLV5608IDWR-ND",
"mouser": "595-TLV5608IDWR"
},
"distributor_check": {
"checked_at": "2026-10-11T15:12:34Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "TLV5608IDWR-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "595-TLV5608IDWR",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "DGND",
"type": "power_in",
"description": "Digital ground for the serial interface and digital logic."
},
{
"number": "2",
"name": "DIN",
"type": "input",
"description": "Digital serial data input; after FS falls, data is shifted in MSB first on the falling edges of SCLK."
},
{
"number": "3",
"name": "SCLK",
"type": "input",
"description": "Serial clock input, with a maximum serial clock frequency of 30 MHz."
},
{
"number": "4",
"name": "FS",
"type": "input",
"description": "Frame sync input; a falling edge starts a write cycle, and in µC mode FS must stay low until all 16 data bits have been transferred."
},
{
"number": "5",
"name": "PRE",
"type": "input",
"description": "Preset input; when driven low and LDAC is asserted, all DAC outputs are driven to the preset register value, and PRE is asynchronous to the clock."
},
{
"number": "6",
"name": "OUTE",
"type": "output",
"description": "DAC output E, a buffered rail-to-rail output (gain of two) that can reliably drive a 2-kΩ load with 100-pF load capacitance."
},
{
"number": "7",
"name": "OUTF",
"type": "output",
"description": "DAC output F, a buffered rail-to-rail output (gain of two) that can reliably drive a 2-kΩ load with 100-pF load capacitance."
},
{
"number": "8",
"name": "OUTG",
"type": "output",
"description": "DAC output G, a buffered rail-to-rail output (gain of two) that can reliably drive a 2-kΩ load with 100-pF load capacitance."
},
{
"number": "9",
"name": "OUTH",
"type": "output",
"description": "DAC output H, a buffered rail-to-rail output (gain of two) that can reliably drive a 2-kΩ load with 100-pF load capacitance."
},
{
"number": "10",
"name": "AGND",
"type": "power_in",
"description": "Analog ground for the DAC and output circuitry."
},
{
"number": "11",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply, specified at 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation, and must come up before DVDD for correct power-on reset."
},
{
"number": "12",
"name": "OUTA",
"type": "output",
"description": "DAC output A, a buffered rail-to-rail output (gain of two) that can reliably drive a 2-kΩ load with 100-pF load capacitance."
},
{
"number": "13",
"name": "OUTB",
"type": "output",
"description": "DAC output B, a buffered rail-to-rail output (gain of two) that can reliably drive a 2-kΩ load with 100-pF load capacitance."
},
{
"number": "14",
"name": "OUTC",
"type": "output",
"description": "DAC output C, a buffered rail-to-rail output (gain of two) that can reliably drive a 2-kΩ load with 100-pF load capacitance."
},
{
"number": "15",
"name": "OUTD",
"type": "output",
"description": "DAC output D, a buffered rail-to-rail output (gain of two) that can reliably drive a 2-kΩ load with 100-pF load capacitance."
},
{
"number": "16",
"name": "REF",
"type": "input",
"description": "Voltage reference input, buffered and high impedance, with a range of 0 V to AVDD."
},
{
"number": "17",
"name": "MODE",
"type": "input",
"description": "DSP/µC mode select: high selects µC mode, and not connected (NC) selects DSP mode."
},
{
"number": "18",
"name": "LDAC",
"type": "input",
"description": "Load DAC input; DAC outputs are only updated while LDAC is low, and it is an asynchronous input."
},
{
"number": "19",
"name": "DOUT",
"type": "output",
"description": "Digital serial data output that repeats the DIN data with a 16-clock-cycle delay when enabled, for daisy-chaining."
},
{
"number": "20",
"name": "DVDD",
"type": "power_in",
"description": "Digital power supply, specified at 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation, and must come up after AVDD."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet gives the pin-to-channel mapping for OUTA–OUTH only as a grouped range (pins 6-9 and 1; Package and orderable match confirmed: TLV5608IDWR is the 20-pin SOIC (DW) variant, 2000-piece large; Power-supply range values in the pin descriptions for AVDD and DVDD come from the recommended operat"
],
"pages_sent": 25,
"cost_usd": 0.105,
"at": "2026-10-11T15:12:17"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/tlv5608",
"pages": 25,
"sha256": "5201b308030f0178",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 20,
"described": 20,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "tlv5608idwr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.3,
12.8,
2.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",
"checked": "2026-10-11",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "tlv5608idwr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.3,
12.8,
2.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "65add04f72a9ea644d1761f207a50346d3be7a809d798706e522eaeaa400c7dc",
"checked": "2026-10-11",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}