# TLV4082QDBVRQ1

**Texas Instruments** · Comparators · SOT-23-6

TLV4082QDBVRQ1 from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | V+ | power_in | Supply voltage input that must be connected to a 1.5-V to 5.5-V supply, with a 0.1-µF ceramic capacitor placed close to the pin (required for V+ < 1.5 V). |
| 2 | OUT1 | output | Output for IN1 that is driven low when IN1 falls below VIT-; it is push-pull on the TLV4062 and open-drain on the TLV4082, where it can be pulled up to 5.5 V independent of V+ and requires a pullup resistor. |
| 3 | OUT2 | output | Output for IN2 that is driven low when IN2 falls below VIT-; it is push-pull on the TLV4062 and open-drain on the TLV4082, where it can be pulled up to 5.5 V independent of V+ and requires a pullup resistor. |
| 4 | IN2 | input | Voltage monitoring input connected through an external resistor divider; OUT2 is asserted when the voltage at this pin drops below the threshold VIT-. |
| 5 | GND | power_in | Ground reference pin for the device. |
| 6 | IN1 | input | Voltage monitoring input connected through an external resistor divider; OUT1 is asserted when the voltage at this pin drops below the threshold VIT-. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Amplifiers/Comparators |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply range | VDD | 1.5 |  | 5.5 | V |  | 5 |
| Supply current, VDD = 3.3 V, no load | IDD |  | 2.09 | 5.8 | µA | VDD = 3.3 V, no load | 5 |
| Supply current, VDD = 5.5 V, no load | IDD |  | 2.29 | 6.5 | µA | VDD = 5.5 V, no load | 5 |
| Input current | I(INx) | -15 |  | 15 | nA | V(INx) = 0 V or VDD | 5 |
| Low-level output voltage, VDD >= 1.5 V | VOL |  |  | 0.25 | V | VDD >= 1.5 V, ISINK = 0.4 mA | 5 |
| Low-level output voltage, VDD >= 2.7 V | VOL |  |  | 0.25 | V | VDD >= 2.7 V, ISINK = 2 mA | 5 |
| Low-level output voltage, VDD >= 4.5 V | VOL |  |  | 0.3 | V | VDD >= 4.5 V, ISINK = 3.2 mA | 5 |
| Open-drain output leakage current | Ilkg(OD) | -250 |  | 250 | nA | High impedance, V(INx) = V(OUTx) = 5.5 V | 5 |
| Propagation delay INx rising to OUTx | tPD(r) |  |  | 5.5 | µs | INx transitions between 0 V and 1.3 V | 6 |
| Propagation delay INx falling to OUTx | tPD(f) |  |  | 10 | µs | INx transitions between 0 V and 1.3 V | 6 |
| Recommended power-supply voltage | VDD | 1.5 |  | 5.5 | V |  | 4 |
| Recommended input voltage IN1, IN2 | VIN | 0 |  | 5.5 | V |  | 4 |
| Recommended output voltage (open-drain only) OUT1, OUT2 | VOUT | 0 |  | 5.5 | V |  | 4 |
| Pullup resistor (open-drain only) | RPU | 1.5 |  | 10000 | kΩ |  | 4 |
| Output current OUT1, OUT2 | IOUT | -5 |  | 5 | mA |  | 4 |
| Recommended junction temperature | TJ | -40 | 25 | 125 | °C |  | 4 |
| Recommended input capacitor | CIN |  | 0.1 |  | µF |  | 4 |
| Absolute maximum supply voltage VDD | VDD | -0.3 |  | 7 | V |  | 4 |
| Absolute maximum voltage OUT1, OUT2 (open-drain only) | VOUT | -0.3 |  | 7 | V |  | 4 |
| Absolute maximum voltage IN1, IN2 | VIN | -0.3 |  | 7 | V |  | 4 |
| Absolute maximum current IN1, IN2 | IIN |  |  | 10 | mA |  | 4 |
| Absolute maximum current OUT1, OUT2 | IOUT | -20 |  | 20 | mA |  | 4 |
| Absolute maximum operating junction temperature | TJ | -40 |  | 125 | °C |  | 4 |
| Absolute maximum storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Rising input threshold voltage | VIT+ |  | 1.194 |  | V | V(INx) rising | 5 |
| Rising threshold accuracy | VIT+ | -1 |  | 1 | % |  | 5 |
| Falling input threshold voltage | VIT- |  | 1.134 |  | V | V(INx) falling | 5 |
| Falling threshold accuracy | VIT- | -1 |  | 1 | % |  | 5 |
| In-built hysteresis | VHYS |  | 60 |  | mV |  | 5 |
| Power-on-reset voltage | V(POR) |  | 0.8 |  | V | VOL (max) = 0.2 V, IOL = 15 µA | 5 |
| Startup delay | tSD |  | 570 |  | µs |  | 6 |
| Junction-to-ambient thermal resistance (DBV) | RθJA |  | 193.9 |  | °C/W |  | 5 |
| Junction-to-case (top) thermal resistance (DBV) | RθJC(top) |  | 134.5 |  | °C/W |  | 5 |
| Junction-to-board thermal resistance (DBV) | RθJB |  | 39 |  | °C/W |  | 5 |
| Junction-to-top characterization parameter (DBV) | ψJT |  | 30.4 |  | °C/W |  | 5 |
| Junction-to-board characterization parameter (DBV) | ψJB |  | 38.5 |  | °C/W |  | 5 |

## CAD (KiCad official)

- Symbol: `TLV4082QDBVRQ1`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `tlv4082qdbvrq1-etched.step` / `tlv4082qdbvrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv4082qdbvrq1.step` / `tlv4082qdbvrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tlv4082-q1.pdf) (29 pp, sha256 `33fb0a2d2c4251a9`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlv4082qdbvrq1-datasheet.pdf)