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Contents

README

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TLV320DAC3203IRGER

Texas Instruments · Audio Amplifiers · QFN-24-EP(4x4)

TLV320DAC3203IRGER from Texas Instruments, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MCLK input Master clock input, accepts frequencies from 0.512 MHz to 50 MHz.
2 BCLK bidirectional Primary audio serial data bus bit clock, configurable as input or output.
3 WCLK bidirectional Primary audio serial data bus word clock, configurable as input or output.
4 DIN/MFP1 input Primary: audio serial data bus data input; secondary: digital microphone input or general purpose input.
5 DOUT/MFP2 output Primary: audio serial data bus data output; secondary: general purpose output, clock output, or interrupt outputs.
6 DMDIN/MFP3/SCLK input Primary (SPI_Select = 1): SPI serial clock; secondary: digital microphone input, headset detect input, or audio serial data bus secondary interface input.
7 SCL/SS input I2C serial clock when SPI_SELECT = 0; SPI chip select when SPI_SELECT = 1.
8 SDA/MOSI bidirectional I2C data pin when SPI_SELECT = 0; SPI master output slave input when SPI_SELECT = 1.
9 DMCLK/MFP4/MISO output Primary (SPI_Select = 1): serial data output; secondary: digital microphone clock output, general purpose output, or audio interface outputs.
10 HPR output Right high-power headphone output driver capable of driving 14.4 Ω to 32 Ω loads.
11 LDOin power_in LDO input supply and headphone power supply, voltage range 1.9 V to 3.6 V.
12 HPL output Left high-power headphone output driver capable of driving 14.4 Ω to 32 Ω loads.
13 AVdd power_in Analog voltage supply input 1.5 V to 1.95 V when A-LDO disabled, or LDO filtering output when A-LDO enabled.
14 AVss power_in Analog ground supply.
15 INL input Left analog bypass input with common-mode input range 0.75 V to 0.9 V.
16 INR input Right analog bypass input with common-mode input range 0.75 V to 0.9 V.
17 REF output Reference voltage output for filtering, selectable as 0.75 V or 0.9 V depending on mode.
18 MICBIAS output Microphone bias voltage output, selectable from 1.04 V to 2.5 V depending on mode selection.
19 SPI_SELECT input Control mode select pin: logic 1 = SPI mode, logic 0 = I2C mode.
20 RESET input Reset input, active low; asynchronously resets all device registers.
21 DVss power_in Digital ground and chip-substrate connection.
22 DVdd power_in Digital voltage supply, range 1.26 V to 1.95 V; minimum 1.65 V required for PLL operation.
23 IOVss power_in I/O ground supply.
24 IOVdd power_in I/O voltage supply, range 1.1 V to 3.6 V.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-24-EP(4x4)
Category Amplifiers/Comparators
Pins 25

CAD (KiCad official)

  • Symbol: TLV320DAC3203IRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tlv320dac3203irger-etched.step / tlv320dac3203irger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv320dac3203irger.step / tlv320dac3203irger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 ec71170483907615, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF