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TLV320AIC3106IRGZT
Public Made by Adomby adom
Texas Instruments Audio Interface ICs, VQFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLV320AIC3106IRGZT
Texas Instruments · Audio Interface ICs · VQFN-48(7x7)
TLV320AIC3106IRGZT from Texas Instruments, in a VQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCL | bidirectional | I2C serial clock or GPIO |
| 2 | SDA | bidirectional | I2C serial data input/output or GPIO |
| 3 | LINE1LP | input | MIC1 or Line1 analog input, left positive in single-ended or fully differential configurations |
| 4 | LINE1LM | input | MIC1 or Line1 analog input, left negative in single-ended or fully differential configurations |
| 5 | LINE1RP | input | MIC1 or Line1 analog input, right positive in single-ended or fully differential configurations |
| 6 | LINE1RM | input | MIC1 or Line1 analog input, right negative in single-ended or fully differential configurations |
| 7 | LINE2LP | input | MIC2 or Line2 analog input, left positive in single-ended or fully differential configurations |
| 8 | LINE2LM | input | MIC2 or Line2 analog input, left negative in single-ended or fully differential configurations |
| 9 | LINE2RP | input | MIC2 or Line2 analog input, right positive in single-ended or fully differential configurations |
| 10 | LINE2RM | input | MIC2 or Line2 analog input, right negative in single-ended or fully differential configurations |
| 11 | MIC3L | input | MIC3 left input or multifunction input |
| 12 | MICDET | input | Microphone detect input |
| 13 | MICBIAS | output | Microphone bias voltage output |
| 14 | MIC3R | input | MIC3 right input or multifunction input |
| 15 | AVSS_ADC | power_in | Analog ADC ground supply, 0 V |
| 16 | DRVDD | power_in | ADC analog and output driver voltage supply, 2.7 V to 3.6 V |
| 17 | DRVDD | power_in | ADC analog and output driver voltage supply, 2.7 V to 3.6 V |
| 18 | HPLOUT | output | High-power output driver left positive |
| 19 | HPLCOM | output | High-power output driver left negative or multifunctional |
| 20 | DRVSS | power_in | Analog output driver ground supply, 0 V |
| 21 | DRVSS | power_in | Analog output driver ground supply, 0 V |
| 22 | HPRCOM | output | High-power output driver right negative or multifunctional |
| 23 | HPROUT | output | High-power output driver right positive |
| 24 | DRVDD | power_in | ADC analog and output driver voltage supply, 2.7 V to 3.6 V |
| 25 | AVDD_DAC | power_in | Analog DAC voltage supply, 2.7 V to 3.6 V |
| 26 | AVSS_DAC | power_in | Analog DAC ground supply, 0 V |
| 27 | MONO_LOP | output | Mono line output positive |
| 28 | MONO_LOM | output | Mono line output negative |
| 29 | LEFT_LOP | output | Left line output positive |
| 30 | LEFT_LOM | output | Left line output negative |
| 31 | RIGHT_LOP | output | Right line output positive |
| 32 | RIGHT_LOM | output | Right line output negative |
| 33 | RESET | input | Reset input, active low |
| 34 | GPIO2 | bidirectional | General-purpose I/O #2, can function as digital microphone data input, PLL clock input, or audio serial data bus bit clock |
| 35 | GPIO1 | bidirectional | General-purpose I/O #1, can function as PLL clock output, AGC noise flag, or audio serial data bus word clock |
| 36 | DVDD | power_in | Digital core voltage supply, 1.65 V to 1.95 V |
| 37 | MCLK | input | Master clock input, supports 512 kHz to 50 MHz |
| 38 | BCLK | input | Audio serial data bus bit clock input or output |
| 39 | WCLK | input | Audio serial data bus word clock input or output |
| 40 | DIN | input | Audio serial data bus data input |
| 41 | DOUT | output | Audio serial data bus data output |
| 42 | DVSS | power_in | Digital core and I/O ground supply, 0 V |
| 43 | SELECT | input | Control mode select, 1 for SPI or 0 for I2C |
| 44 | IOVDD | power_in | I/O voltage supply, 1.1 V to 3.6 V |
| 45 | MFP0 | input | Multifunction pin #0 for SPI chip select or GPIO or I2C address bit 0 |
| 46 | MFP1 | input | Multifunction pin #1 for SPI serial clock or GPIO or I2C address bit 1 |
| 47 | MFP2 | input | Multifunction pin #2 for SPI MISO output or GPIO |
| 48 | MFP3 | input | Multifunction pin #3 for SPI MOSI input or GPIO or audio serial data input |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48(7x7) |
| Category | Interface |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
TLV320AIC3106IRGZT - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
tlv320aic3106irgzt-etched.step/tlv320aic3106irgzt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv320aic3106irgzt.step/tlv320aic3106irgzt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (111 pp, sha256
ef5e99dabca91925, retrieved 2026-10-05, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).