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TLV320ADC6120IRTER

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TI Interface ICs, WQFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TLV320ADC6120IRTER

TI · Interface ICs · WQFN-20-EP(3x3)

TLV320ADC6120IRTER from TI, in a WQFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1P input Analog input 1P pin.
2 IN1M input Analog input 1M pin.
3 IN2P_GPI1 input Analog input 2P pin or general-purpose digital input 1 (multipurpose functions such as digital microphone data, PLL input clock source), referenced to AVDD.
4 IN2M_GPO1 bidirectional Analog input 2M pin or general-purpose digital output 1 (multipurpose functions such as digital microphone clock, interrupt).
5 VSS power_in Device ground internally shorted to thermal pad; short this package corner pin directly to the board ground plane.
6 SDOUT output Audio serial data interface bus output.
7 BCLK bidirectional Audio serial data interface bus bit clock.
8 FSYNC bidirectional Audio serial data interface bus frame synchronization signal.
9 IOVDD power_in Digital I/O power supply, 1.8 V or 3.3 V nominal.
10 VSS power_in Device ground internally shorted to thermal pad; short this package corner pin directly to the board ground plane.
11 GPIO1 bidirectional General-purpose digital input/output 1 (multipurpose functions such as digital microphone clock or data, PLL input clock source, interrupt).
12 SDA bidirectional Data pin for I2C control bus.
13 SCL input Clock pin for I2C control bus.
14 DREG power_out Digital regulator output for digital core supply (1.5 V nominal); connect 10-µF and 0.1-µF low ESR capacitors in parallel to VSS.
15 VSS power_in Device ground internally shorted to thermal pad; short this package corner pin directly to the board ground plane.
16 AVDD power_in Analog power supply, 1.8 V or 3.3 V nominal.
17 AREG power_out Analog on-chip regulator output (1.8 V nominal) or external 1.8 V analog supply input; connect 10-µF and 0.1-µF low ESR capacitors in parallel to analog ground.
18 VREF power_in Analog reference voltage filter output; connect a 1-µF capacitor to analog ground (AVSS).
19 MICBIAS_GPI2 bidirectional MICBIAS output or general-purpose digital input 2 (digital microphone data, PLL input clock source); if used as MICBIAS connect a 1-µF capacitor to analog ground.
20 VSS power_in Device ground internally shorted to thermal pad; short this package corner pin directly to the board ground plane.
21 Thermal Pad (VSS) power_in Thermal pad shorted to internal device ground; short directly to the board ground plane.

Key specifications

Parameter Value
Manufacturer TI
Package WQFN-20-EP(3x3)
Category Interface ICs
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AVSS supply voltage AVDD -0.3 3.9 V 5
AREG to AVSS supply voltage AREG -0.3 2 V 5
IOVDD to VSS supply voltage IOVDD -0.3 3.9 V IOVDD to VSS (thermal pad) 5
Ground voltage difference AVSS to VSS -0.3 0.3 V AVSS to VSS (thermal pad) 5
Analog input pin voltage -0.3 V Analog input pins voltage to AVSS; max AVDD + 0.3 5
Digital input voltage (except IN2P_GPI1, MICBIAS_GPI2) -0.3 V to VSS; max IOVDD + 0.3 5
Digital input voltage IN2P_GPI1, MICBIAS_GPI2 -0.3 V to VSS; max AVDD + 0.3 5
Operating ambient temperature TA -40 125 °C 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
ESD HBM V(ESD) -2000 2000 V Human-body model, ANSI/ESDA/JEDEC JS-001 5
ESD CDM V(ESD) -500 500 V Charged-device model, JESD22-C101 5
Analog supply voltage, 3.3-V operation AVDD 3 3.3 3.6 V AREG generated by on-chip regulator 6
Analog supply voltage, 1.8-V operation AVDD, AREG 1.7 1.8 1.9 V AREG internal regulator shutdown 6
IO supply voltage, 3.3-V operation IOVDD 3 3.3 3.6 V IOVDD to VSS 6
IO supply voltage, 1.8-V operation IOVDD 1.65 1.8 1.95 V IOVDD to VSS 6
Operating ambient temperature TA -40 125 °C 6
MCLK input clock frequency 36.864 MHz GPIOx or GPIx used as MCLK input 6
I2C bus capacitance, standard/fast-mode Cb 400 pF SCL and SDA, standard-mode and fast-mode 6
I2C bus capacitance, fast-mode plus Cb 550 pF SCL and SDA, fast-mode plus 6
Digital output load capacitance CL 20 50 pF 6
Junction-to-ambient thermal resistance RθJA 55.9 °C/W RTE (WQFN) 20 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 33.1 °C/W 6
Junction-to-board thermal resistance RθJB 23.4 °C/W 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 16.7 °C/W 6
Signal-to-noise ratio, A-weighted SNR 115 122 dB IN1 differential, DRE enabled (DRE_LVL = -36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance, AVDD 3.3 V 7
Signal-to-noise ratio, A-weighted SNR 106 112 dB IN1 differential, DRE disabled, 2.5-kΩ input impedance, 0-dB channel gain, AVDD 3.3 V 7
Total harmonic distortion + noise THD+N -95 -80 dB IN1 differential, -1-dB full-scale input, DRE enabled, 2.5-kΩ input impedance, AVDD 3.3 V 7
Digital high-pass filter cutoff 12 Hz First-order IIR, -3-dB point (default) 8
MICBIAS load regulation 0 0.6 1 % MICBIAS programmed to VREF or VREF × 1.096, measured up to max load 9
Low-level input voltage VIL -0.3 0.8 V All digital pins except IN2P_GPI1, MICBIAS_GPI2, SDA, SCL, IOVDD 3.3-V operation 9
High-level input voltage VIH 2 V All digital pins except IN2P_GPI1, MICBIAS_GPI2, SDA, SCL, IOVDD 3.3-V operation; max IOVDD + 0.3 9
Low-level output voltage VOL 0.4 V IOL = -2 mA, IOVDD 3.3-V operation 9
High-level output voltage VOH 2.4 V IOH = 2 mA, IOVDD 3.3-V operation 9
Input leakage high IIH -5 0.1 5 µA All digital pins except IN2P_GPI1 and MICBIAS_GPI2, input = IOVDD 9
Input leakage low IIL -5 0.1 5 µA All digital pins except IN2P_GPI1 and MICBIAS_GPI2, input = 0 V 9
MICBIAS current drive 5 mA 9
Digital input capacitance CIN 5 pF All digital pins 10
Output data sample rate 7.35 768 kHz Programmable 8
Channel gain range 0 42 dB Programmable range with 0.5-dB steps 7
BCLK period t(BCLK) 40 ns 12
BCLK to SDOUT delay td(SDOUT-BCLK) 3 18 ns 50% of BCLK to 50% of SDOUT 12
PDMCLK clock frequency f(PDMCLK) 0.768 6.144 MHz 13
I2C SCL clock frequency, fast-mode fSCL 0 400 kHz FAST-MODE 11
AVDD sleep current IAVDD 5 µA All external clocks stopped, AVDD = 3.3 V, internal AREG 10
AVDD current, 2-channel, 48 kHz, PLL on, DRE disabled IAVDD 12.4 mA AVDD = 3.3 V, internal AREG 10

CAD (KiCad official)

  • Symbol: TLV320ADC6120IRTER
  • Footprint: Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm
  • 3D model: WQFN-20-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tlv320adc6120irter-etched.step / tlv320adc6120irter-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv320adc6120irter.step / tlv320adc6120irter.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TI datasheet (129 pp, sha256 007f3c53dd8458f5, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF