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Ray tlv3012aqdckrq1: specified limits as data (metadata.characteristics, 38 rows from the datasheet) 77354f7 11d ago

TLV3012AQDCKRQ1

Texas Instruments · Comparators · SC-70-6

TLV3012AQDCKRQ1 from Texas Instruments, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Comparator output; on the TLV3012 it is a push-pull stage, and the absolute maximum output voltage range is -0.5 V to (V+) + 0.5 V with a 10 mA output short-circuit current limit.
2 V- power_in Negative (lowest) power supply; the supply voltage VS = (V+) - (V-) is specified from 1.8 V to 5.5 V.
3 IN+ input Non-inverting comparator input; the recommended input voltage range is (V-) - 0.2 V to (V+) + 0.2 V.
4 IN- input Inverting comparator input; the recommended input voltage range is (V-) - 0.2 V to (V+) + 0.2 V.
5 REF output Integrated 1.242 V voltage reference output, stable with up to 10 nF capacitive load and sourcing or sinking up to 0.5 mA (typical 500 µA).
6 V+ power_in Positive (highest) power supply; the supply voltage VS = (V+) - (V-) is specified from 1.8 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-6
Category Amplifiers/Comparators
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VS -0.5 7 V VS = (V+) – (V–) 4
Input pins voltage (absolute maximum) -0.5 7 V IN+, IN–; referenced to (V–) 4
Open-drain output voltage (absolute maximum) -0.5 7 V OUT open-drain; referenced to (V–) 4
Push-pull output voltage (absolute maximum) -0.5 V OUT push-pull; upper limit printed as (V+) + 0.5 V 4
Output short-circuit current 10 mA Short to (V–) or (V+) 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD human body model V(ESD) -2000 2000 V HBM, per AEC Q100-002 4
ESD charged device model V(ESD) -1000 1000 V CDM, per AEC Q100-011 4
Supply voltage (recommended) VS 1.8 5.5 V VS = (V+) – (V–) 4
Input voltage range -0.2 V Referenced to (V–); upper limit printed as (V+) + 0.2 V 4
Open-drain output voltage range -0.2 V Open-drain; referenced to (V–); upper limit printed as (V+) 4
Ambient temperature TA -40 125 °C 4
Input offset voltage VOS -6 0.3 6 mV VCM = (V–) 5
Input offset voltage over temperature VOS -9 9 mV VCM = (V–); TA = –40°C 至 +125°C 5
Input offset voltage drift dVIO/dT -12 12 µV/°C VCM = (V–); TA = –40°C 至 +125°C 5
Power-supply rejection ratio PSRR 100 1000 µV/V VCM = (V–); VS = 1.8V 至 5.5V; TA = –40°C 至 +125°C 5
Input hysteresis voltage VHYS 2 6 8 mV TA = -40°C 至 +125°C 5
Input bias current IB -10 4.5 10 pA VCM = VS /2 5
Input offset current IOS -10 1 10 pA VCM = VS /2 5
Common-mode voltage range VCM-Range -0.2 V VS = 1.8V 至 5.5V; referenced to (V–); upper limit printed as (V+) + 0.2 V 5
Common-mode rejection ratio CMRR 60 74 dB VCM = (V–) + 1.5V 至 (V+) + 0.2V; VS = 5.5V 5
Common-mode rejection ratio (extended range) CMRR 54 62 dB VCM = (V–) - 0.2V 至 (V+) + 0.2V; VS = 5.5V 5
Reference accuracy -0.25 0.25 % 5
Reference accuracy -1.5 1.5 % 5
Reference voltage VOUT 1.223 1.242 1.26 V 5
Reference voltage drift dVOUT/dT 40 100 ppm/℃ TA = –40℃ 至 +125℃ 5
Load regulation, sourcing dVOUT/dILOAD 0.36 1 mV/mA 0mA < ISOURCE ≤ 0.5mA 5
Line regulation dVOUT/dVS 10 100 µV/V 1.8V ≤ VS ≤ 5.5V 5
Low output voltage swing (VOL) VOL 160 200 mV VS = 5V; ISINK = 5mA; TA = -40°C 至 +125°C 5
High output voltage swing (VOH, push-pull only) VOH 90 200 mV VS = 5V; ISOURCE = 5mA; TA = –40°C 至 +125°C 5
Quiescent current per comparator IQ 2.8 5 µA Output logic high 6
Quiescent current per comparator over temperature IQ 7 µA Output logic high; TA = –40°C 至 +125°C 6
Thermal resistance, junction-to-ambient RθJA 169.8 °C/W DCK (SC-70, 6-pin) package 4
Thermal resistance, junction-to-case (top) RθJC(top) 120.5 °C/W DCK (SC-70, 6-pin) package 4
Thermal resistance, junction-to-board RθJB 63.2 °C/W DCK (SC-70, 6-pin) package 4
Junction-to-top characterization parameter ψJT 45.9 °C/W DCK (SC-70, 6-pin) package 4
Junction-to-board characterization parameter ψJB 63 °C/W DCK (SC-70, 6-pin) package 4

CAD (KiCad official)

  • Symbol: TLV3012AQDCKRQ1
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6 (KiCad packages3D, STEP)
  • 3D model files: tlv3012aqdckrq1-etched.step / tlv3012aqdckrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv3012aqdckrq1.step / tlv3012aqdckrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 a8530424c8741b27, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF