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TLV27L2QDRQ1
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Texas Instruments Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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tlv27l2qdrq1: specified limits as data (metadata.characteristics, 46 rows from the datasheet)
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TLV27L2QDRQ1
Texas Instruments · Operational Amplifier · SOIC-8
TLV27L2QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT A | output | Output of channel A. |
| 2 | -IN A | input | Inverting input of channel A. |
| 3 | +IN A | input | Noninverting input of channel A. |
| 4 | V- | power_in | Negative (lowest) power supply; the datasheet describes this as the lowest supply rail and the single-supply operating ground reference. |
| 5 | +IN B | input | Noninverting input of channel B. |
| 6 | -IN B | input | Inverting input of channel B. |
| 7 | OUT B | output | Output of channel B. |
| 8 | V+ | power_in | Positive (highest) power supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Single supply voltage | VS | 2.7 | 16 | V | Single supply | 4 | |
| Dual supply voltage | VS | 1.35 | 8 | V | Dual supply, printed as ±1.35 V to ±8 V | 4 | |
| Operating free-air temperature | TA | -40 | 125 | °C | 4 | ||
| Input common-mode voltage | VIC | -0.2 | V | Maximum printed as VS – 1.2 V | 4 | ||
| Supply voltage | VS | 16.5 | V | Absolute maximum | 4 | ||
| Output current | IO | 100 | mA | 4 | |||
| Maximum junction temperature | TJ | 150 | °C | 4 | |||
| Operating free-air temperature | TA | -40 | 125 | °C | 4 | ||
| Lead temperature | 300 | °C | 1/16 inch from case for 10 seconds | 4 | |||
| Storage temperature | Tstg | -65 | 125 | °C | 4 | ||
| Human-body model ESD | V(ESD) | -2000 | 2000 | V | HBM per AEC Q100-002 | 4 | |
| Charged-device model ESD | V(ESD) | -1000 | 1000 | V | CDM per AEC Q100-011 | 4 | |
| Input offset voltage | VIO | 0.5 | 5 | mV | 25°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 | |
| Input offset voltage | VIO | 7 | mV | Full range (–40°C to 125°C); VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 | ||
| Common-mode rejection ratio | CMRR | 71 | 86 | dB | 25°C; VIC = 0 V to VS – 1.2 V, RS = 50 Ω | 5 | |
| Common-mode rejection ratio | CMRR | 70 | dB | Full range; VIC = 0 V to VS – 1.2 V, RS = 50 Ω | 5 | ||
| Large-signal differential voltage amplification | AVD | 80 | 100 | dB | 25°C; VS = 2.7 V, 5 V; VO(PP) = VS/2, RL = 100 kΩ | 5 | |
| Large-signal differential voltage amplification | AVD | 77 | dB | Full range; VS = 2.7 V, 5 V; VO(PP) = VS/2, RL = 100 kΩ | 5 | ||
| Large-signal differential voltage amplification | AVD | 77 | 82 | dB | 25°C; VS = ±5 V | 5 | |
| Large-signal differential voltage amplification | AVD | 74 | dB | Full range; VS = ±5 V | 5 | ||
| Input offset current | IIO | 1 | 60 | pA | ≤ 25°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 | |
| Input offset current | IIO | 100 | pA | ≤ 70°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 | ||
| Input offset current | IIO | 1000 | pA | ≤ 125°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 | ||
| Input bias current | IIB | 1 | 60 | pA | ≤ 25°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 | |
| Input bias current | IIB | 200 | pA | ≤ 70°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 | ||
| Input bias current | IIB | 1000 | pA | ≤ 125°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 | ||
| Quiescent current (per channel) | IQ | 7 | 11 | µA | 25°C; VO = VS/2 | 5 | |
| Quiescent current (per channel) | IQ | 16 | µA | Full range; VO = VS/2 | 5 | ||
| Power supply rejection ratio | PSRR | 74 | 82 | dB | 25°C; no load, VS = 2.7 V to 16 V, VIC = VS/2 | 5 | |
| Power supply rejection ratio | PSRR | 70 | dB | Full range; no load, VS = 2.7 V to 16 V, VIC = VS/2 | 5 | ||
| Output voltage swing from rail | VO | 160 | 200 | mV | 25°C; VIC = VS/2, IOL = 100 µA, VS = 2.7 V | 5 | |
| Output voltage swing from rail | VO | 220 | mV | Full range; VIC = VS/2, IOL = 100 µA, VS = 2.7 V | 5 | ||
| Output voltage swing from rail | VO | 85 | 120 | mV | 25°C; VIC = VS/2, IOL = 100 µA, VS = 5 V | 5 | |
| Output voltage swing from rail | VO | 200 | mV | Full range; VIC = VS/2, IOL = 100 µA, VS = 5 V | 5 | ||
| Output voltage swing from rail | VO | 50 | 120 | mV | 25°C; VIC = VS/2, IOL = 100 µA, VS = ±5 V | 5 | |
| Output voltage swing from rail | VO | 150 | mV | Full range; VIC = VS/2, IOL = 100 µA, VS = ±5 V | 5 | ||
| Output voltage swing from rail | VO | 420 | 800 | mV | 25°C; VIC = VS/2, IOL = 500 µA, VS = 5 V | 5 | |
| Output voltage swing from rail | VO | 900 | mV | Full range; VIC = VS/2, IOL = 500 µA, VS = 5 V | 5 | ||
| Output voltage swing from rail | VO | 200 | 400 | mV | 25°C; VIC = VS/2, IOL = 500 µA, VS = ±5 V | 5 | |
| Output voltage swing from rail | VO | 500 | mV | Full range; VIC = VS/2, IOL = 500 µA, VS = ±5 V | 5 | ||
| Slew rate at unity gain | SR | 0.05 | V/µs | –40°C; VO(pp) = 1 V, RL = 100 kΩ, CL = 50 pF | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 122.2 | °C/W | D (SOIC) 8-pin | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 70.5 | °C/W | D (SOIC) 8-pin | 4 | ||
| Junction-to-board thermal resistance | RθJB | 62.5 | °C/W | D (SOIC) 8-pin | 4 | ||
| Junction-to-top characterization parameter | ψJT | 22.3 | °C/W | D (SOIC) 8-pin | 4 | ||
| Junction-to-board characterization parameter | ψJB | 62 | °C/W | D (SOIC) 8-pin | 4 |
CAD (KiCad official)
- Symbol:
TLV27L2QDRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tlv27l2qdrq1-etched.step/tlv27l2qdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv27l2qdrq1.step/tlv27l2qdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
60e34434dce0ff39, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TLV27L2QDRQ1
**Texas Instruments** · Operational Amplifier · SOIC-8
TLV27L2QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT A | output | Output of channel A. |
| 2 | -IN A | input | Inverting input of channel A. |
| 3 | +IN A | input | Noninverting input of channel A. |
| 4 | V- | power_in | Negative (lowest) power supply; the datasheet describes this as the lowest supply rail and the single-supply operating ground reference. |
| 5 | +IN B | input | Noninverting input of channel B. |
| 6 | -IN B | input | Inverting input of channel B. |
| 7 | OUT B | output | Output of channel B. |
| 8 | V+ | power_in | Positive (highest) power supply. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Single supply voltage | VS | 2.7 | | 16 | V | Single supply | 4 |
| Dual supply voltage | VS | 1.35 | | 8 | V | Dual supply, printed as ±1.35 V to ±8 V | 4 |
| Operating free-air temperature | TA | -40 | | 125 | °C | | 4 |
| Input common-mode voltage | VIC | -0.2 | | | V | Maximum printed as VS – 1.2 V | 4 |
| Supply voltage | VS | | | 16.5 | V | Absolute maximum | 4 |
| Output current | IO | | | 100 | mA | | 4 |
| Maximum junction temperature | TJ | | | 150 | °C | | 4 |
| Operating free-air temperature | TA | -40 | | 125 | °C | | 4 |
| Lead temperature | | | | 300 | °C | 1/16 inch from case for 10 seconds | 4 |
| Storage temperature | Tstg | -65 | | 125 | °C | | 4 |
| Human-body model ESD | V(ESD) | -2000 | | 2000 | V | HBM per AEC Q100-002 | 4 |
| Charged-device model ESD | V(ESD) | -1000 | | 1000 | V | CDM per AEC Q100-011 | 4 |
| Input offset voltage | VIO | | 0.5 | 5 | mV | 25°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 |
| Input offset voltage | VIO | | | 7 | mV | Full range (–40°C to 125°C); VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 |
| Common-mode rejection ratio | CMRR | 71 | 86 | | dB | 25°C; VIC = 0 V to VS – 1.2 V, RS = 50 Ω | 5 |
| Common-mode rejection ratio | CMRR | 70 | | | dB | Full range; VIC = 0 V to VS – 1.2 V, RS = 50 Ω | 5 |
| Large-signal differential voltage amplification | AVD | 80 | 100 | | dB | 25°C; VS = 2.7 V, 5 V; VO(PP) = VS/2, RL = 100 kΩ | 5 |
| Large-signal differential voltage amplification | AVD | 77 | | | dB | Full range; VS = 2.7 V, 5 V; VO(PP) = VS/2, RL = 100 kΩ | 5 |
| Large-signal differential voltage amplification | AVD | 77 | 82 | | dB | 25°C; VS = ±5 V | 5 |
| Large-signal differential voltage amplification | AVD | 74 | | | dB | Full range; VS = ±5 V | 5 |
| Input offset current | IIO | | 1 | 60 | pA | ≤ 25°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 |
| Input offset current | IIO | | | 100 | pA | ≤ 70°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 |
| Input offset current | IIO | | | 1000 | pA | ≤ 125°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 |
| Input bias current | IIB | | 1 | 60 | pA | ≤ 25°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 |
| Input bias current | IIB | | | 200 | pA | ≤ 70°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 |
| Input bias current | IIB | | | 1000 | pA | ≤ 125°C; VIC = VS/2, VO = VS/2, RL = 100 kΩ, RS = 50 Ω | 5 |
| Quiescent current (per channel) | IQ | | 7 | 11 | µA | 25°C; VO = VS/2 | 5 |
| Quiescent current (per channel) | IQ | | | 16 | µA | Full range; VO = VS/2 | 5 |
| Power supply rejection ratio | PSRR | 74 | 82 | | dB | 25°C; no load, VS = 2.7 V to 16 V, VIC = VS/2 | 5 |
| Power supply rejection ratio | PSRR | 70 | | | dB | Full range; no load, VS = 2.7 V to 16 V, VIC = VS/2 | 5 |
| Output voltage swing from rail | VO | | 160 | 200 | mV | 25°C; VIC = VS/2, IOL = 100 µA, VS = 2.7 V | 5 |
| Output voltage swing from rail | VO | | | 220 | mV | Full range; VIC = VS/2, IOL = 100 µA, VS = 2.7 V | 5 |
| Output voltage swing from rail | VO | | 85 | 120 | mV | 25°C; VIC = VS/2, IOL = 100 µA, VS = 5 V | 5 |
| Output voltage swing from rail | VO | | | 200 | mV | Full range; VIC = VS/2, IOL = 100 µA, VS = 5 V | 5 |
| Output voltage swing from rail | VO | | 50 | 120 | mV | 25°C; VIC = VS/2, IOL = 100 µA, VS = ±5 V | 5 |
| Output voltage swing from rail | VO | | | 150 | mV | Full range; VIC = VS/2, IOL = 100 µA, VS = ±5 V | 5 |
| Output voltage swing from rail | VO | | 420 | 800 | mV | 25°C; VIC = VS/2, IOL = 500 µA, VS = 5 V | 5 |
| Output voltage swing from rail | VO | | | 900 | mV | Full range; VIC = VS/2, IOL = 500 µA, VS = 5 V | 5 |
| Output voltage swing from rail | VO | | 200 | 400 | mV | 25°C; VIC = VS/2, IOL = 500 µA, VS = ±5 V | 5 |
| Output voltage swing from rail | VO | | | 500 | mV | Full range; VIC = VS/2, IOL = 500 µA, VS = ±5 V | 5 |
| Slew rate at unity gain | SR | 0.05 | | | V/µs | –40°C; VO(pp) = 1 V, RL = 100 kΩ, CL = 50 pF | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 122.2 | | °C/W | D (SOIC) 8-pin | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 70.5 | | °C/W | D (SOIC) 8-pin | 4 |
| Junction-to-board thermal resistance | RθJB | | 62.5 | | °C/W | D (SOIC) 8-pin | 4 |
| Junction-to-top characterization parameter | ψJT | | 22.3 | | °C/W | D (SOIC) 8-pin | 4 |
| Junction-to-board characterization parameter | ψJB | | 62 | | °C/W | D (SOIC) 8-pin | 4 |
## CAD (KiCad official)
- Symbol: `TLV27L2QDRQ1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tlv27l2qdrq1-etched.step` / `tlv27l2qdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv27l2qdrq1.step` / `tlv27l2qdrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlv27l2-q1) (26 pp, sha256 `60e34434dce0ff39`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tlv27l2qdrq1-datasheet.pdf)