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TLV2772IDGKR

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Texas Instruments Operational Amplifier, VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLV2772IDGKR

Texas Instruments · Operational Amplifier · VSSOP-8

TLV2772IDGKR from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Channel 1 output, rail-to-rail; the output current is absolute-maximum rated at ±50 mA and the output may be shorted to either supply within the dissipation limits.
2 1IN− input Channel 1 inverting input, which must stay within the input voltage range of GND to VDD+ −1.3 V (recommended), with input current limited to ±4 mA.
3 1IN+ input Channel 1 non-inverting input, which must stay within the input voltage range of GND to VDD+ −1.3 V (recommended), with input current limited to ±4 mA.
4 GND power_in Ground reference (negative supply) to which all voltages in the datasheet are referenced.
5 2IN+ input Channel 2 non-inverting input, which must stay within the input voltage range of GND to VDD+ −1.3 V (recommended), with input current limited to ±4 mA.
6 2IN− input Channel 2 inverting input, which must stay within the input voltage range of GND to VDD+ −1.3 V (recommended), with input current limited to ±4 mA.
7 2OUT output Channel 2 output, rail-to-rail; the output current is absolute-maximum rated at ±50 mA and the output may be shorted to either supply within the dissipation limits.
8 VDD power_in Positive supply, specified at 2.5 V to 6 V (recommended), with an absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage, TA = 25°C VIO 0.48 2.5 mV VIC = 0, VO = 0, RS = 50 Ω, VDD = ±1.35 V 10
Input offset voltage, full range VIO 0.53 2.7 mV VIC = 0, VO = 0, RS = 50 Ω, VDD = ±1.35 V; full range −40°C to 125°C 10
Input offset current, TA = 25°C IIO 1 60 pA VIC = 0, VO = 0; 25°C 10
Input offset current, full range IIO 2 125 pA VIC = 0, VO = 0, RS = 50 Ω, VDD = ±1.35 V; full range 10
Input bias current, TA = 25°C IIB 2 60 pA RS = 50 Ω; 25°C 10
Input bias current, full range IIB 6 350 pA RS = 50 Ω; full range 10
High-level output voltage, full range VOH 2.5 V IOH = −0.675 mA; full range 10
High-level output voltage, full range VOH 2.1 V IOH = −2.2 mA; full range 10
Low-level output voltage, full range VOL 0.2 V VIC = 1.35 V, IOL = 0.675 mA; full range 10
Low-level output voltage, full range VOL 0.6 V VIC = 1.35 V, IOL = 2.2 mA; full range 10
Large-signal differential voltage amplification, TA = 25°C AVD 20 380 V/mV VIC = 1.35 V, RL = 10 kΩ; 25°C 10
Large-signal differential voltage amplification, full range AVD 13 V/mV VIC = 1.35 V, VO = 0.6 V to 2.1 V, RL = 10 kΩ; full range 10
Common-mode rejection ratio, TA = 25°C CMRR 60 84 dB VIC = 0 to 1.5 V, VO = VDD/2; 25°C 10
Common-mode rejection ratio, full range CMRR 60 82 dB VIC = 0 to 1.5 V, RS = 50 Ω, VO = VDD/2; full range 10
Supply voltage rejection ratio, TA = 25°C kSVR 70 89 dB VDD = 2.7 V to 5 V, VIC = VDD/2; 25°C 10
Supply voltage rejection ratio, full range kSVR 70 84 dB VDD = 2.7 V to 5 V, VIC = VDD/2, no load; full range 10
Supply current (per channel), TA = 25°C IDD 1 2 mA VO = VDD/2, no load; 25°C 10
Supply current (per channel), full range IDD 2 mA VO = VDD/2, no load; full range 10
Slew rate at unity gain, TA = 25°C SR 5 9 V/µs VO(PP) = 0.8 V, CL = 100 pF, RL = 10 kΩ; 25°C 11
Slew rate at unity gain, full range SR 4.7 6 V/µs VO(PP) = 0.8 V, CL = 100 pF, RL = 10 kΩ; full range 11
Input offset voltage, TA = 25°C VIO 0.5 2.5 mV VIC = 0, No load; 25°C 12
Input offset voltage, full range VIO 0.6 2.7 mV VIC = 0, No load, VO = 0; full range 12
Input offset current, TA = 25°C IIO 1 60 pA VIC = 0, VO = 0; 25°C 12
Input offset current, full range IIO 2 125 pA VO = 0, RS = 50 Ω; full range 12
Input bias current, TA = 25°C IIB 2 60 pA RS = 50 Ω, VDD = ±2.5 V; 25°C 12
Input bias current, full range IIB 6 350 pA RS = 50 Ω, VDD = ±2.5 V; full range 12
High-level output voltage, full range VOH 4.8 V IOH = −1.3 mA; full range 12
High-level output voltage, full range VOH 4.4 V IOH = −4.2 mA; full range 12
Low-level output voltage, full range VOL 0.2 V VIC = 2.5 V, IOL = 1.3 mA; full range 12
Low-level output voltage, full range VOL 0.6 V VIC = 2.5 V, IOL = 4.2 mA; full range 12
Large-signal differential voltage amplification, TA = 25°C AVD 20 450 V/mV VIC = 2.5 V, RL = 10 kΩ; 25°C 12
Large-signal differential voltage amplification, full range AVD 13 V/mV VIC = 2.5 V, VO = 1 V to 4 V, RL = 10 kΩ; full range 12
Common-mode rejection ratio, TA = 25°C CMRR 60 96 dB VIC = 0 to 3.7 V, VO = VDD/2; 25°C 12
Common-mode rejection ratio, full range CMRR 60 93 dB VIC = 0 to 3.7 V, RS = 50 Ω, VO = VDD/2; full range 12
Supply voltage rejection ratio, TA = 25°C kSVR 70 89 dB VDD = 2.7 V to 5 V, VIC = VDD/2; 25°C 12
Supply voltage rejection ratio, full range kSVR 70 84 dB VDD = 2.7 V to 5 V, VIC = VDD/2, no load; full range 12
Supply current (per channel), TA = 25°C IDD 1 2 mA VO = VDD/2, no load; 25°C 12
Supply current (per channel), full range IDD 2 mA VO = VDD/2, no load; full range 12
Slew rate at unity gain, TA = 25°C SR 5 10.5 V/µs VO(PP) = 1.5 V, CL = 100 pF, RL = 10 kΩ; 25°C 13
Slew rate at unity gain, full range SR 4.7 6 V/µs VO(PP) = 1.5 V, CL = 100 pF, RL = 10 kΩ; full range 13
Supply voltage VDD 7 V Voltages referenced to GND (Note 1) 5
Input voltage range (any input) VI -0.3 V Any input; upper limit printed as VDD (not numeric) 5
Input current (any input) II -4 4 mA Any input 5
Output current IO -50 50 mA 5
Total current into VDD+ -50 50 mA 5
Total current out of GND -50 50 mA 5
Operating free-air temperature range, I suffix TA -40 125 °C I suffix 5
Storage temperature range Tstg -65 150 °C 5
Lead temperature 260 °C 1.6 mm (1/16 inch) from case for 10 s 5
Supply voltage, recommended VDD 2.5 6 V I suffix 5
Operating free-air temperature, recommended TA -40 125 °C I suffix 5
Continuous total power dissipation, DGK package PD 424 mW TA ≤ 25°C; derating factor 3.4 mW/°C above 25°C 5
Junction-to-ambient thermal resistance θJA 260 °C/W No air flow; JEDEC low-K test PCB (MSOP package label) 39

CAD (KiCad official)

  • Symbol: TLV2772IDGKR
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: tlv2772idgkr-etched.step / tlv2772idgkr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv2772idgkr.step / tlv2772idgkr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (82 pp, sha256 60e1b990cf9adc8a, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF