component

TLV274IPWR

Public Made by Adom

by adom

Texas Instruments Operational Amplifier, TSSOP-14. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

componentamplifiers-comparatorstlv274ipwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

TLV274IPWR

Texas Instruments · Operational Amplifier · TSSOP-14

TLV274IPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Output of channel 1 with rail-to-rail swing from 0V to VDD and maximum output current ±100mA
2 1IN- input Inverting input of channel 1 with common-mode input voltage range 0 to VDD-1.35V
3 1IN+ input Non-inverting input of channel 1 with common-mode input voltage range 0 to VDD-1.35V
4 VDD power_in Positive power supply, 2.7V to 16V single supply or ±1.35V to ±8V dual supply
5 2IN+ input Non-inverting input of channel 2 with common-mode input voltage range 0 to VDD-1.35V
6 2IN- input Inverting input of channel 2 with common-mode input voltage range 0 to VDD-1.35V
7 2OUT output Output of channel 2 with rail-to-rail swing from 0V to VDD and maximum output current ±100mA
8 3OUT output Output of channel 3 with rail-to-rail swing from 0V to VDD and maximum output current ±100mA
9 3IN- input Inverting input of channel 3 with common-mode input voltage range 0 to VDD-1.35V
10 3IN+ input Non-inverting input of channel 3 with common-mode input voltage range 0 to VDD-1.35V
11 GND power_in Ground or negative power supply reference for single supply operation
12 4IN+ input Non-inverting input of channel 4 with common-mode input voltage range 0 to VDD-1.35V
13 4IN- input Inverting input of channel 4 with common-mode input voltage range 0 to VDD-1.35V
14 4OUT output Output of channel 4 with rail-to-rail swing from 0V to VDD and maximum output current ±100mA

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Amplifiers/Comparators
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VIO 0.5 5 mV VIC = VDD/2, RL = 10kΩ, VO = VDD/2, RS = 50Ω; TA = 25°C 6
Input offset voltage VIO 7 mV VIC = VDD/2, RL = 10kΩ, VO = VDD/2, RS = 50Ω; TA = full range 6
Common-mode rejection ratio CMRR 58 70 dB VIC = 0 至 VDD − 1.35V, RS = 50Ω, VDD = 2.7V; TA = 25°C 6
Common-mode rejection ratio CMRR 55 dB VIC = 0 至 VDD − 1.35V, RS = 50Ω, VDD = 2.7V; TA = full range 6
Common-mode rejection ratio CMRR 65 80 dB VIC = 0 至 VDD − 1.35V, RS = 50Ω, VDD = 5V; TA = 25°C 6
Common-mode rejection ratio CMRR 62 dB VIC = 0 至 VDD − 1.35V, RS = 50Ω, VDD = 5V; TA = full range 6
Common-mode rejection ratio CMRR 69 85 dB VIC = -5V 至 VDD − 1.35V, RS = 50Ω, VDD = ±5V; TA = 25°C 6
Common-mode rejection ratio CMRR 66 dB VIC = -5V 至 VDD − 1.35V, RS = 50Ω, VDD = ±5V; TA = full range 6
Large-signal differential voltage gain AVD 97 106 dB VO(PP) = VDD/2, RL = 10kΩ, VDD = 2.7V; TA = 25°C 6
Large-signal differential voltage gain AVD 76 dB VO(PP) = VDD/2, RL = 10kΩ, VDD = 2.7V; TA = full range 6
Large-signal differential voltage gain AVD 100 110 dB VO(PP) = VDD/2, RL = 10kΩ, VDD = 5V; TA = 25°C 6
Large-signal differential voltage gain AVD 86 dB VO(PP) = VDD/2, RL = 10kΩ, VDD = 5V; TA = full range 6
Large-signal differential voltage gain AVD 100 115 dB VO(PP) = VDD/2, RL = 10kΩ, VDD = ±5V; TA = 25°C 6
Large-signal differential voltage gain AVD 90 dB VO(PP) = VDD/2, RL = 10kΩ, VDD = ±5V; TA = full range 6
Input offset current IIO 1 60 pA VDD = 5V, VIC = VDD/2, VO = VDD/2, RS = 50Ω; TA = 25°C 6
Input offset current IIO 100 pA VDD = 5V, VIC = VDD/2, VO = VDD/2, RS = 50Ω; TA = 70°C 6
Input offset current IIO 1000 pA VDD = 5V, VIC = VDD/2, VO = VDD/2, RS = 50Ω; TA = 125°C 6
Input bias current IIB 1 60 pA VDD = 5V, VIC = VDD/2, VO = VDD/2, RS = 50Ω; TA = 25°C 6
Input bias current IIB 100 pA VDD = 5V, VIC = VDD/2, VO = VDD/2, RS = 50Ω; TA = 70°C 6
Input bias current IIB 1000 pA VDD = 5V, VIC = VDD/2, VO = VDD/2, RS = 50Ω; TA = 125°C 6
High-level output voltage VOH 2.55 2.58 V VIC = VDD/2, IOH = -1mA, VDD = 2.7V; TA = 25°C 7
High-level output voltage VOH 2.48 V VIC = VDD/2, IOH = -1mA, VDD = 2.7V; TA = full range 7
High-level output voltage VOH 4.9 4.93 V VIC = VDD/2, IOH = -1mA, VDD = 5V; TA = 25°C 7
High-level output voltage VOH 4.85 V VIC = VDD/2, IOH = -1mA, VDD = 5V; TA = full range 7
High-level output voltage VOH 4.92 4.96 V VIC = VDD/2, IOH = -1mA, VDD = ±5V; TA = 25°C 7
High-level output voltage VOH 4.9 V VIC = VDD/2, IOH = -1mA, VDD = ±5V; TA = full range 7
High-level output voltage VOH 1.9 2.1 V VIC = VDD/2, IOH = -5mA, VDD = 2.7V; TA = 25°C 7
High-level output voltage VOH 1.5 V VIC = VDD/2, IOH = -5mA, VDD = 2.7V; TA = full range 7
High-level output voltage VOH 4.6 4.68 V VIC = VDD/2, IOH = -5mA, VDD = 5V; TA = 25°C 7
High-level output voltage VOH 4.5 V VIC = VDD/2, IOH = -5mA, VDD = 5V; TA = full range 7
High-level output voltage VOH 4.7 4.84 V VIC = VDD/2, IOH = -5mA, VDD = ±5V; TA = 25°C 7
High-level output voltage VOH 4.65 V VIC = VDD/2, IOH = -5mA, VDD = ±5V; TA = full range 7
Low-level output voltage VOL 0.1 0.15 V VIC = VDD/2, IOH = 1mA, VDD = 2.7V; TA = 25°C 7
Low-level output voltage VOL 0.22 V VIC = VDD/2, IOH = 1mA, VDD = 2.7V; TA = full range 7
Low-level output voltage VOL 0.05 0.1 V VIC = VDD/2, IOH = 1mA, VDD = 5V; TA = 25°C 7
Low-level output voltage VOL 0.15 V VIC = VDD/2, IOH = 1mA, VDD = 5V; TA = full range 7
Low-level output voltage VOL -4.95 -4.92 V VIC = VDD/2, IOH = 1mA, VDD = ±5V; TA = 25°C 7
Low-level output voltage VOL -4.9 V VIC = VDD/2, IOH = 1mA, VDD = ±5V; TA = full range 7
Low-level output voltage VOL 0.5 0.7 V VIC = VDD/2, IOH = 5mA, VDD = 2.7V; TA = 25°C 7
Low-level output voltage VOL 1.1 V VIC = VDD/2, IOH = 5mA, VDD = 2.7V; TA = full range 7
Low-level output voltage VOL 0.28 0.4 V VIC = VDD/2, IOH = 5mA, VDD = 5V; TA = 25°C 7
Low-level output voltage VOL 0.5 V VIC = VDD/2, IOH = 5mA, VDD = 5V; TA = full range 7
Low-level output voltage VOL -4.84 -4.7 V VIC = VDD/2, IOH = 5mA, VDD = ±5V; TA = 25°C 7
Low-level output voltage VOL -4.65 V VIC = VDD/2, IOH = 5mA, VDD = ±5V; TA = full range 7
Output current, positive rail IO 4 mA VO = 0.5V relative to supply rail, VDD = 2.7V; TA = 25°C 7
Output current, negative rail IO 5 mA VO = 0.5V relative to supply rail, VDD = 2.7V; TA = 25°C 7
Output current, positive rail IO 7 mA VO = 0.5V relative to supply rail, VDD = 5V; TA = 25°C 7
Output current, negative rail IO 8 mA VO = 0.5V relative to supply rail, VDD = 5V; TA = 25°C 7
Supply current (per channel) IDD 470 560 µA VO = VDD/2, VDD = 2.7V; TA = 25°C 8
Supply current (per channel) IDD 550 660 µA VO = VDD/2, VDD = 5V; TA = 25°C 8
Supply current (per channel) IDD 625 800 µA VO = VDD/2, VDD = 10V; TA = 25°C 8
Supply current (per channel) IDD 1000 µA VO = VDD/2, VDD = 10V; TA = full range 8
Power supply rejection ratio PSRR 70 80 dB VDD = 2.7V 至 16V, VIC = VDD/2, no load; TA = 25°C 8
Power supply rejection ratio PSRR 65 dB VDD = 2.7V 至 16V, VIC = VDD/2, no load; TA = full range 8
Slew rate at unity gain SR 1.35 2.1 V/µs VO(PP) = VDD/2, CL = 50pF, RL = 10kΩ, VDD = 2.7V; TA = 25°C 8
Slew rate at unity gain SR 1 V/µs VO(PP) = VDD/2, CL = 50pF, RL = 10kΩ, VDD = 2.7V; TA = full range 8
Slew rate at unity gain SR 1.45 2.4 V/µs VO(PP) = VDD/2, CL = 50pF, RL = 10kΩ, VDD = 5V; TA = 25°C 8
Slew rate at unity gain SR 1.2 V/µs VO(PP) = VDD/2, CL = 50pF, RL = 10kΩ, VDD = 5V; TA = full range 8
Slew rate at unity gain SR 1.8 2.6 V/µs VO(PP) = VDD/2, CL = 50pF, RL = 10kΩ, VDD = ±5V; TA = 25°C 8
Slew rate at unity gain SR 1.3 V/µs VO(PP) = VDD/2, CL = 50pF, RL = 10kΩ, VDD = ±5V; TA = full range 8

CAD (KiCad official)

  • Symbol: TLV274IPWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: tlv274ipwr-etched.step / tlv274ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv274ipwr.step / tlv274ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 4836bd271e5a3a2e, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF