component

TLV272IP

Public Made by Adom

by adom

Texas Instruments Pre-ordered Chips, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icstlv272ipfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
tlv272ip / README.md
History Download
Ray Publish 0.1.0 7b7f92b 13d ago

TLV272IP

Texas Instruments · Pre-ordered Chips · PDIP-8

TLV272IP from Texas Instruments, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Output, channel 1.
2 1IN- input Inverting input, channel 1.
3 1IN+ input Noninverting input, channel 1.
4 GND power_in Negative (lowest) supply or ground (for single-supply operation).
5 2IN+ input Noninverting input, channel 2.
6 2IN- input Inverting input, channel 2.
7 2OUT output Output, channel 2.
8 VDD power_in Positive (highest) supply.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 16.5 V 6
Input current II -10 10 mA 6
Output current IO -100 100 mA 6
Operating free-air temperature (I-suffix) TA -40 125 °C I-suffix 6
Junction temperature TJ 150 °C 6
Storage temperature Tstg -65 150 °C 6
Supply voltage, single-supply VDD 2.7 16 V Single-supply 6
Supply voltage, split-supply VDD 1.35 8 V Split-supply (±) 6
Common-mode input voltage VICR 0 V Max is VDD − 1.35 V 6
Operating free-air temperature (I-suffix) TA -40 125 °C I-suffix 6
Input offset voltage VIO 0.5 5 mV 25°C; VIC = VDD/2, RL = 10 kΩ, VO = VDD/2, RS = 50 Ω 8
Input offset voltage VIO 7 mV Full range; VIC = VDD/2, RL = 10 kΩ, VO = VDD/2, RS = 50 Ω 8
Common-mode rejection ratio CMRR 58 70 dB 25°C; VIC = 0 to VDD − 1.35 V, RS = 50 Ω, VDD = 2.7 V 8
Common-mode rejection ratio CMRR 55 dB Full range; VIC = 0 to VDD − 1.35 V, RS = 50 Ω, VDD = 2.7 V 8
Common-mode rejection ratio CMRR 65 80 dB 25°C; VIC = 0 to VDD − 1.35 V, RS = 50 Ω, VDD = 5 V 8
Common-mode rejection ratio CMRR 62 dB Full range; VIC = 0 to VDD − 1.35 V, RS = 50 Ω, VDD = 5 V 8
Common-mode rejection ratio CMRR 69 85 dB 25°C; VIC = -5 V to VDD − 1.35 V, RS = 50 Ω, VDD = ±5 V 8
Common-mode rejection ratio CMRR 66 dB Full range; VIC = -5 V to VDD − 1.35 V, RS = 50 Ω, VDD = ±5 V 8
Large-signal differential voltage amplification AVD 97 106 dB 25°C; VO(PP) = VDD/2, RL = 10 kΩ, VDD = 2.7 V 8
Large-signal differential voltage amplification AVD 76 dB Full range; VO(PP) = VDD/2, RL = 10 kΩ, VDD = 2.7 V 8
Large-signal differential voltage amplification AVD 100 110 dB 25°C; VO(PP) = VDD/2, RL = 10 kΩ, VDD = 5 V 8
Large-signal differential voltage amplification AVD 86 dB Full range; VO(PP) = VDD/2, RL = 10 kΩ, VDD = 5 V 8
Large-signal differential voltage amplification AVD 100 115 dB 25°C; VO(PP) = VDD/2, RL = 10 kΩ, VDD = ±5 V 8
Large-signal differential voltage amplification AVD 90 dB Full range; VO(PP) = VDD/2, RL = 10 kΩ, VDD = ±5 V 8
Input offset current IIO 1 60 pA 25°C; VDD = 5 V, VIC = VDD/2, VO = VDD/2, RS = 50 Ω 8
Input bias current IIB 1 60 pA 25°C; VDD = 5 V, VIC = VDD/2, VO = VDD/2, RS = 50 Ω 8
High-level output voltage VOH 2.55 2.58 V 25°C; VIC = VDD/2, IOH = -1 mA, VDD = 2.7 V 9
High-level output voltage VOH 2.48 V Full range; VIC = VDD/2, IOH = -1 mA, VDD = 2.7 V 9
High-level output voltage VOH 4.9 4.93 V 25°C; VIC = VDD/2, IOH = -1 mA, VDD = 5 V 9
High-level output voltage VOH 4.85 V Full range; VIC = VDD/2, IOH = -1 mA, VDD = 5 V 9
High-level output voltage VOH 4.92 4.96 V 25°C; VIC = VDD/2, IOH = -1 mA, VDD = ±5 V 9
High-level output voltage VOH 4.9 V Full range; VIC = VDD/2, IOH = -1 mA, VDD = ±5 V 9
High-level output voltage VOH 1.9 2.1 V 25°C; VIC = VDD/2, IOH = -5 mA, VDD = 2.7 V 9
High-level output voltage VOH 4.6 4.68 V 25°C; VIC = VDD/2, IOH = -5 mA, VDD = 5 V 9
High-level output voltage VOH 4.7 4.84 V 25°C; VIC = VDD/2, IOH = -5 mA, VDD = ±5 V 9
Low-level output voltage VOL 0.1 0.15 V 25°C; VIC = VDD/2, IOL = 1 mA, VDD = 2.7 V 9
Low-level output voltage VOL 0.22 V Full range; VIC = VDD/2, IOL = 1 mA, VDD = 2.7 V 9
Low-level output voltage VOL 0.05 0.1 V 25°C; VIC = VDD/2, IOL = 1 mA, VDD = 5 V 9
Low-level output voltage VOL 0.15 V Full range; VIC = VDD/2, IOL = 1 mA, VDD = 5 V 9
Low-level output voltage VOL -4.95 -4.92 V 25°C; VIC = VDD/2, IOL = 1 mA, VDD = ±5 V 9
Low-level output voltage VOL 0.5 0.7 V 25°C; VIC = VDD/2, IOL = 5 mA, VDD = 2.7 V 9
Low-level output voltage VOL 0.28 0.4 V 25°C; VIC = VDD/2, IOL = 5 mA, VDD = 5 V 9
Low-level output voltage VOL -4.84 -4.7 V 25°C; VIC = VDD/2, IOL = 5 mA, VDD = ±5 V 9
Output current, positive rail IO 4 mA 25°C; VO = 0.5 V from rail, VDD = 2.7 V 9
Output current, negative rail IO 5 mA 25°C; VO = 0.5 V from rail, VDD = 2.7 V 9
Output current, positive rail IO 7 mA 25°C; VO = 0.5 V from rail, VDD = 5 V 9
Output current, negative rail IO 8 mA 25°C; VO = 0.5 V from rail, VDD = 5 V 9
Supply current (per channel) IDD 470 560 µA 25°C; VO = VDD/2, VDD = 2.7 V 10
Supply current (per channel) IDD 550 660 µA 25°C; VO = VDD/2, VDD = 5 V 10
Supply current (per channel) IDD 625 800 µA 25°C; VO = VDD/2, VDD = 10 V 10
Temperature drift of input offset voltage αVIO 2 µV/°C 25°C 8
Phase margin φm 65 ° 25°C; RL = 2 kΩ, CL = 10 pF 10
Equivalent input noise voltage Vn 39 nV/√Hz 25°C; f = 1 kHz 10
Junction-to-ambient thermal resistance (PDIP) RθJA 49.2 °C/W PDIP (P), 8 pins 7
Junction-to-case (top) thermal resistance (PDIP) RθJC(top) 39.4 °C/W PDIP (P), 8 pins 7
Junction-to-board thermal resistance (PDIP) RθJB 26.4 °C/W PDIP (P), 8 pins 7
Junction-to-top characterization parameter (PDIP) ψJT 15.4 °C/W PDIP (P), 8 pins 7
Junction-to-board characterization parameter (PDIP) ψJB 26.3 °C/W PDIP (P), 8 pins 7

CAD (KiCad official)

  • Symbol: TLV272IP
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: tlv272ip-etched.step / tlv272ip-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv272ip.step / tlv272ip.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 08d1cc5a8cc926f3, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF