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TLV271IDR

Public Made by Adom

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Texas Instruments Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TLV271IDR

Texas Instruments · Operational Amplifier · SOIC-8

TLV271IDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection; can be left floating.
2 IN- input Negative (inverting) input of the operational amplifier.
3 IN+ input Positive (noninverting) input of the operational amplifier.
4 GND power_in Negative (lowest) supply or ground for single-supply operation; split supply is ±1.35 V to ±8 V.
5 NC unconnected No internal connection; can be left floating.
6 OUT output Rail-to-rail output of the operational amplifier.
7 VDD power_in Positive (highest) supply; single-supply range is 2.7 V to 16 V, absolute maximum 16.5 V.
8 NC unconnected No internal connection; can be left floating.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Amplifiers
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VIO 0.5 5 mV VIC = VDD/2, RL = 10 kΩ, VO = VDD/2, RS = 50 Ω, 25°C 8
Input offset voltage, full range VIO 7 mV Full range 8
CMRR CMRR 58 70 dB VIC = 0 to VDD − 1.35 V, RS = 50 Ω, VDD = 2.7 V, 25°C 8
CMRR CMRR 65 80 dB VIC = 0 to VDD − 1.35 V, RS = 50 Ω, VDD = 5 V, 25°C 8
CMRR CMRR 69 85 dB VIC = -5 V to VDD − 1.35 V, RS = 50 Ω, VDD = ±5 V, 25°C 8
Large-signal differential voltage amplification AVD 97 106 dB VO(PP) = VDD/2, RL = 10 kΩ, VDD = 2.7 V, 25°C 8
Large-signal differential voltage amplification AVD 100 110 dB VO(PP) = VDD/2, RL = 10 kΩ, VDD = 5 V, 25°C 8
Large-signal differential voltage amplification AVD 100 115 dB VO(PP) = VDD/2, RL = 10 kΩ, VDD = ±5 V, 25°C 8
Input offset current IIO 1 60 pA VDD = 5 V, VIC = VDD/2, VO = VDD/2, RS = 50 Ω, 25°C 8
Input offset current IIO 1000 pA VDD = 5 V, VIC = VDD/2, VO = VDD/2, RS = 50 Ω, 125°C 8
Input bias current IIB 1 60 pA VDD = 5 V, VIC = VDD/2, VO = VDD/2, RS = 50 Ω, 25°C 8
Input bias current IIB 1000 pA VDD = 5 V, VIC = VDD/2, VO = VDD/2, RS = 50 Ω, 125°C 8
High-level output voltage VOH 4.9 4.93 V VIC = VDD/2, IOH = -1 mA, VDD = 5 V, 25°C 9
High-level output voltage VOH 4.6 4.68 V VIC = VDD/2, IOH = -5 mA, VDD = 5 V, 25°C 9
Low-level output voltage VOL 0.05 0.1 V VIC = VDD/2, IOH = 1 mA, VDD = 5 V, 25°C 9
Low-level output voltage VOL 0.28 0.4 V VIC = VDD/2, IOH = 5 mA, VDD = 5 V, 25°C 9
Supply current (per channel) IDD 470 560 µA VO = VDD/2, VDD = 2.7 V, 25°C 10
Supply current (per channel) IDD 550 660 µA VO = VDD/2, VDD = 5 V, 25°C 10
Supply current (per channel) IDD 625 800 µA VO = VDD/2, VDD = 10 V, 25°C 10
Supply current (per channel), full range IDD 1000 µA VO = VDD/2, VDD = 10 V, Full range 10
Supply voltage rejection ratio PSRR 70 80 dB VDD = 2.7 V to 16 V, VIC = VDD/2, no load, 25°C 10
Slew rate at unity gain SR 1.45 2.4 V/µs VO(PP) = VDD/2, CL = 50 pF, RL = 10 kΩ, VDD = 5 V, 25°C 10
Slew rate at unity gain SR 1.35 2.1 V/µs VO(PP) = VDD/2, CL = 50 pF, RL = 10 kΩ, VDD = 2.7 V, 25°C 10
Supply voltage, single-supply VDD 2.7 16 V Single-supply 6
Operating free-air temperature, I-suffix TA -40 125 °C I-suffix 6
Supply voltage VDD 16.5 V 6
Input current II -10 10 mA 6
Output current IO -100 100 mA 6
Operating temperature, I-suffix TA -40 125 °C I-suffix 6
Junction temperature TJ 150 °C 6
Storage temperature Tstg -65 150 °C 6
Junction-to-ambient thermal resistance RθJA 127.2 °C/W D (SOIC), 8 pins 7
Junction-to-case (top) thermal resistance RθJC(top) 71.6 °C/W D (SOIC), 8 pins 7
Junction-to-board thermal resistance RθJB 68.2 °C/W D (SOIC), 8 pins 7
Junction-to-top characterization parameter ψJT 22 °C/W D (SOIC), 8 pins 7
Junction-to-board characterization parameter ψJB 67.6 °C/W D (SOIC), 8 pins 7

CAD (KiCad official)

  • Symbol: TLV271IDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tlv271idr-etched.step / tlv271idr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv271idr.step / tlv271idr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 08d1cc5a8cc926f3, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF