component

TLV2548QDWR

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADCs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversiontlv2548qdwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1mo ago
viewers tlv2548qdwr: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json Set visibility: public · Ray 1mo ago
README.md Initial commit: component/tlv2548qdwr · Ray 1mo ago
tlv2548qdwr-etched.glb tlv2548qdwr: factory component page (tier=lcsc) · Ray 1mo ago
tlv2548qdwr-etched.step tlv2548qdwr: factory component page (tier=lcsc) · Ray 1mo ago
tlv2548qdwr-hero.glb tlv2548qdwr: hero GLB from the etched model (keeps the MPN mark) · Ray 29d ago
tlv2548qdwr-hero.overlay.json Publish 0.1.0 · Ray 1mo ago
tlv2548qdwr.glb Publish 0.1.0 · Ray 1mo ago
tlv2548qdwr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tlv2548qdwr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tlv2548qdwr.lbr Publish 0.1.0 · Ray 1mo ago
tlv2548qdwr.step Publish 0.1.0 · Ray 1mo ago

TLV2548QDWR

Texas Instruments · Analog To Digital Converters (ADCs) · SOIC-20-300mil

TLV2548QDWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDO tri_state The 3-state serial output carries the A/D conversion result MSB (D15) first, and SDO is high-impedance when CS is high.
2 SDI input Serial data input takes the MSB (D15) first, where D15-D12 are decoded as one of 16 commands and latched on SCLK rising edges (or falling edges when FS is used).
3 SCLK input Input serial clock from the host clocks SDI into the input register and may also source the conversion clock; the device supports CPOL = 0.
4 EOC/(INT) output Programmable as EOC, which goes low at the end of sampling until conversion is complete (conversion mode 00 only), or as INT, whose falling edge signals data ready and is cleared by the following CS↓ or FS.
5 VCC power_in Positive supply voltage, specified for a single supply from 3 Vdc to 5.5 Vdc.
6 A0 input Analog signal input that is internally multiplexed; the driving source impedance should be less than or equal to 1 kΩ, or CSTART or long sampling should be used for higher impedance.
7 A1 input Analog signal input that is internally multiplexed; the driving source impedance should be less than or equal to 1 kΩ, or CSTART or long sampling should be used for higher impedance.
8 A2 input Analog signal input that is internally multiplexed; the driving source impedance should be less than or equal to 1 kΩ, or CSTART or long sampling should be used for higher impedance.
9 A3 input Analog signal input that is internally multiplexed; the driving source impedance should be less than or equal to 1 kΩ, or CSTART or long sampling should be used for higher impedance.
10 A4 input Analog signal input that is internally multiplexed; the driving source impedance should be less than or equal to 1 kΩ, or CSTART or long sampling should be used for higher impedance.
11 A5 input Analog signal input that is internally multiplexed; the driving source impedance should be less than or equal to 1 kΩ, or CSTART or long sampling should be used for higher impedance.
12 A6 input Analog signal input that is internally multiplexed; the driving source impedance should be less than or equal to 1 kΩ, or CSTART or long sampling should be used for higher impedance.
13 A7 input Analog signal input that is internally multiplexed; the driving source impedance should be less than or equal to 1 kΩ, or CSTART or long sampling should be used for higher impedance.
14 CSTART input Controls the start of sampling and conversion: sampling begins at the falling edge and ends at the rising edge while CS is high, and the pin should be tied to VCC if not used.
15 GND power_in Ground return for the internal circuitry; all voltage measurements are referenced to GND.
16 PWDN input When low, the analog and reference circuits are powered down, and the device restarts via an active CS, FS, or CSTART after PWDN returns to logic one.
17 FS input DSP frame sync input that indicates the start of a serial data frame; it should be tied to VCC if not used.
18 REFM input External reference input or internal reference decoupling terminal, and the reference-minus side of the input voltage range.
19 REFP input External reference input or internal reference decoupling terminal; the maximum input range is REFP minus REFM, with 10 µF and 0.1 µF shunt capacitors between REFP and REFM.
20 CS input Chip select: a high-to-low transition resets the internal 4-bit counter, enables SDI, and removes SDO from 3-state, and SDI is disabled after 16 clock edges or a low-to-high transition of CS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category ADC/DAC/Data Conversion
Pins 20

CAD (KiCad official)

  • Symbol: TLV2548QDWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: tlv2548qdwr-etched.step / tlv2548qdwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv2548qdwr.step / tlv2548qdwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 7ec6c3c44c39e2be, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF