TLV2548CPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDO	output	The 3-state serial output presents the A/D conversion result MSB first and is held in high impedance when CS is high.
2	SDI	input	The serial data input takes 16-bit words MSB (D15) first, with D(15-12) decoded as the command and a 12-bit configuration field following write commands.
3	SCLK	input	The input serial clock from the host processor clocks SDI into the input register and may also serve as the source of the conversion clock.
4	EOC/(INT)	output	This pin is the end-of-conversion output (low from end of sampling until data are ready) or, when programmed, the interrupt output whose falling edge signals data ready.
5	VCC	power_in	The positive supply voltage operates from a single 2.7 V to 5.5 V supply.
6	A0	input	This analog signal input is internally multiplexed and the driving source impedance should be less than or equal to 1 kΩ.
7	A1	input	This analog signal input is internally multiplexed and the driving source impedance should be less than or equal to 1 kΩ.
8	A2	input	This analog signal input is internally multiplexed and the driving source impedance should be less than or equal to 1 kΩ.
9	A3	input	This analog signal input is internally multiplexed and the driving source impedance should be less than or equal to 1 kΩ.
10	A4	input	This analog signal input is internally multiplexed and the driving source impedance should be less than or equal to 1 kΩ.
11	A5	input	This analog signal input is internally multiplexed and the driving source impedance should be less than or equal to 1 kΩ.
12	A6	input	This analog signal input is internally multiplexed and the driving source impedance should be less than or equal to 1 kΩ.
13	A7	input	This analog signal input is internally multiplexed and the driving source impedance should be less than or equal to 1 kΩ.
14	CSTART	input	This asynchronous input controls the start and length of sampling on the selected channel, with the sampling period set by its low time, and must be tied to VCC if not used.
15	GND	power_in	This is the ground return for the internal circuitry, and all voltage measurements are referenced to GND.
16	PWDN	input	When held at logic zero both the analog and reference circuits are powered down, and the device restarts by an active CS, FS or CSTART after returning to logic one.
17	FS	input	The DSP frame sync input indicates the start of a serial data frame and must be tied to VCC if not used.
18	REFM	input	This pin is the external reference input or internal reference decoupling and must be tied to analog ground when the internal reference is used.
19	REFP	input	This pin is the external reference input or internal reference decoupling with 10 µF and 0.1 µF shunt capacitors to REFM, and the maximum input range is the REFP to REFM voltage difference.
20	CS	input	The chip select input resets the internal 4-bit counter, enables SDI and removes SDO from 3-state when taken high-to-low.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Data Acquisition
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	2.7	3.3	5.5	V		20
Analog input voltage		0			V	see Note 4; max printed as VCC	20
High-level control input voltage	VIH	2.1			V		20
Low-level control input voltage	VIL			0.6	V		20
Delay time CS falling edge to FS rising edge	td(CSL-FSH)	0.5			SCLKs	see Figure 16	20
Delay time 16th SCLK falling edge to CS rising edge (FS=1) or 17th rising edge (FS active)	td(SCLK-CSH)	0.5			SCLKs	see Figures 16 and 19	20
Setup time FS rising edge before SCLK falling edge	tsu(FSH-SCLKL)	20			ns	see Figure 16	20
Hold time FS high after SCLK falling edge	th(FSH-SCLKL)	30			ns	see Figure 16	20
Pulse width CS high time	twH(CS)	100			ns	see Figures 16 and 19	20
Pulse width FS high time	twH(FS)	0.75		1	SCLKs	see Figure 16	20
SCLK cycle time	tc(SCLK)	75		10000	ns	VCC = 2.7 V to 3.6 V	20
SCLK cycle time	tc(SCLK)	50		10000	ns	VCC = 4.5 V to 5.5 V	20
Pulse width SCLK low time	twL(SCLK)	0.4		0.6	SCLKs	see Figures 16 and 19	21
Pulse width SCLK high time	twH(SCLK)	0.4		0.6	SCLKs	see Figures 16 and 19	21
Setup time SDI valid before SCLK edge	tsu(DI-SCLK)	25			ns	FS is active or FS=1; see Figures 16 and 19	21
Hold time SDI valid after SCLK edge	th(DI-SCLK)	5			ns	FS is active or FS=1; see Figure 16	21
Delay time CS falling edge to SDO valid	td(CSL-DOV)			25	ns	see Figures 16 and 19	21
Delay time FS falling edge to SDO valid	td(FSL-DOV)			25	ns	see Figure 16	21
Delay time 17th SCLK rising edge (FS active) or 16th falling edge (FS=1) to EOC falling edge	td(SCLK-EOCL)	45			ns	see Figures 16 and 19	21
Delay time CS falling edge or FS rising edge to INT rising edge	td(CSL-INTH)			50	ns	see Figures 16, 17, 18 and 19; printed value preceded by 1 in table	21
Delay time CS rising edge to CSTART falling edge	td(CSH-CSTARTL)	100			ns	see Figures 17 and 18	21
Delay time CSTART rising edge to EOC falling edge	td(CSTARTH-EOCL)			50	ns	see Figures 17 and 18; printed value preceded by 1 in table	21
Operating free-air temperature TLV2548C	TA	0		70	°C	TLV2544C/TLV2548C	21
Supply voltage	VCC	-0.3		6.5	V	GND to VCC	20
Analog input voltage range		-0.3			V	upper limit printed as VCC + 0.3 V	20
Digital input voltage range		-0.3			V	upper limit printed as VCC + 0.3 V	20
Operating virtual junction temperature range	TJ	-55		150	°C		20
Storage temperature range	Tstg	-65		150	°C		20
Lead temperature				260	°C	1.6 mm (1/16 inch) from case for 10 seconds	20
Power rating, 20 PW package				977	mW	TA ≤ 25°C	20
High-level output voltage	VOH	2.4			V	VCC = 5.5 V, IOH = -0.2 mA at 25 pF load	22
Low-level output voltage	VOL			0.4	V	VCC = 5.5 V, IOL = 0.8 mA at 25 pF load	22
Low-level output voltage	VOL			0.1	V	VCC = 2.7 V, IOL = 20 µA at 25 pF load	22
Off-state output current (high-impedance state)	IOZ		1	2.5	µA	VO = VCC, CS = VCC	22
Off-state output current (high-impedance state)	IOZ	-2.5	-1		µA	VO = 0, CS = VCC	22
High-level input current	IIH		0.005	2.5	µA	VI = VCC	22
Low-level input current	IIL		-0.005	2.5	µA	VI = 0 V	22
Operating supply current, normal, external reference	ICC			1.1	mA	CS at 0 V, Ext ref, VCC = 4.5 V to 5.5 V	22
Operating supply current, normal, external reference	ICC			1	mA	CS at 0 V, Ext ref, VCC = 2.7 V to 3.3 V	22
Operating supply current, normal short sampling, internal reference	ICC			2.1	mA	CS at 0 V, Int ref, VCC = 4.5 V to 5.5 V	22
Operating supply current, normal short sampling, internal reference	ICC			1.6	mA	CS at 0 V, Int ref, VCC = 2.7 V to 3.3 V	22
Power down supply current	ICC(PD)		0.1	1	µA	for all digital inputs, VCC = 4.5 V to 5.5 V, Ext clock	22
Auto power-down current for all digital inputs	ICC(AUTOPWDN)			1	µA	VCC = 4.5 V to 5.5 V, Ext clock, Ext ref	22
Internal reference voltage, REFP−REFM		3.85	4	4.15	V	VCC = 5.5 V, VREF SELECT = 4 V	23
Internal reference voltage, REFP−REFM		1.925	2	2.075	V	VCC = 5.5 V, VREF SELECT = 2 V	23
Internal reference start-up time				20	ms	VCC = 5.5 V, 2.7 V with 10 µF compensation cap	23
Internal reference temperature coefficient			16	40	PPM/°C	VCC = 2.7 V to 5.5 V; max specified by design	23
Integral linearity error (INL)	EL	-1		1	LSB		24
Differential linearity error (DNL)	ED	-1		1	LSB	See Note 5	24
Offset error	EO	-2.5		2.5	LSB	See Note 5	24
Full scale error	EFS	-1.6		3.5	LSB	See Note 5	24
Conversion time, internal OSC	t(conv)	2.33	3.5	3.86	µs	Internal OSC	24
Signal-to-noise ratio + distortion	SINAD	69	70		dB	fI = 12 kHz at 200 KSPS, C and I suffix	23
Total harmonic distortion	THD		-82	-76	dB	fI = 12 kHz at 200 KSPS	23
Spurious free dynamic range	SFDR		-84	-75	dB	fI = 12 kHz at 200 KSPS	23
Effective number of bits	ENOB		11.6		Bits	fI = 12 kHz at 200 KSPS	23
Power rating derating factor above TA = 25°C, 20 PW package			7.8		mW/°C	20 PW package, above TA = 25°C	20

CAD (KiCad official)

Symbol: TLV2548CPWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: tlv2548cpwr-etched.step / tlv2548cpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv2548cpwr.step / tlv2548cpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (51 pp, sha256 0baf06c23013ca49, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TLV2548CPWR

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