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TLV2442AQDRQ1

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Texas Instruments Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLV2442AQDRQ1

Texas Instruments · Operational Amplifier · SOIC-8

TLV2442AQDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Output of amplifier 1 of the dual TLV2442 op amp.
2 1IN− input Inverting input of amplifier 1.
3 1IN+ input Non-inverting input of amplifier 1.
4 VDD−/GND power_in Negative supply rail, which is ground in single-supply operation.
5 2IN+ input Non-inverting input of amplifier 2.
6 2IN− input Inverting input of amplifier 2.
7 2OUT output Output of amplifier 2 of the dual TLV2442 op amp.
8 VDD+ power_in Positive supply rail.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage (TLV244xA) VIO 300 950 µV VDD = 3 V; TA = 25°C; VIC = 1.5 V, VO = 1.5 V, RS = 50 Ω 5
Input offset voltage (TLV244xA) VIO 1600 µV VDD = 3 V; Full range; VIC = 1.5 V, VO = 1.5 V, RS = 50 Ω 5
Input offset current IIO 150 pA VDD = 3 V; Full range; VIC = 1.5 V, VO = 1.5 V, RS = 50 Ω 5
Input bias current IIB 260 pA VDD = 3 V; Full range; VIC = 1.5 V, VO = 1.5 V, RS = 50 Ω 5
Common-mode input voltage range VICR 0.2 2 V VDD = 3 V; Full range; /VIO/ ≤ 8 mV, RS = 50 Ω 5
High-level output voltage VOH 2.25 V VDD = 3 V; Full range; IO = –3 mA 5
Low-level output voltage VOL 1 V VDD = 3 V; Full range; VIC = 1.5 V, IO = 3 mA 5
Large-signal differential voltage amplification AVD 0.7 1 V/mV VDD = 3 V; TA = 25°C; RL = 600 Ω; VO = 1 V to 2 V 5
Large-signal differential voltage amplification AVD 0.4 V/mV VDD = 3 V; Full range; RL = 600 Ω; VO = 1 V to 2 V 5
Common-mode rejection ratio CMRR 65 75 dB VDD = 3 V; TA = 25°C; VIC = VICR MIN, VO = VDD/2, RS = 50 Ω 5
Common-mode rejection ratio CMRR 50 dB VDD = 3 V; Full range; VIC = VICR MIN, VO = VDD/2, RS = 50 Ω 5
Supply-voltage rejection ratio (ΔVDD±/ΔVIO) kSVR 80 95 dB VDD = 3 V; TA = 25°C; VDD = 2.7 V to 8 V, VIC = VDD/2, No load 5
Supply-voltage rejection ratio (ΔVDD±/ΔVIO) kSVR 80 dB VDD = 3 V; Full range; VDD = 2.7 V to 8 V, VIC = VDD/2, No load 5
Supply current (per channel) IDD 725 1100 µA VDD = 3 V; TA = 25°C; VO = 1.5 V, No load 5
Supply current (per channel) IDD 1100 µA VDD = 3 V; Full range; VO = 1.5 V, No load 5
Slew rate at unity gain SR 0.65 1.3 V/µs VDD = 3 V; TA = 25°C; VO = 1 V to 2 V, RL = 600 Ω, CL = 100 pF 6
Slew rate at unity gain SR 0.4 V/µs VDD = 3 V; Full range; VO = 1 V to 2 V, RL = 600 Ω, CL = 100 pF 6
Input offset voltage (TLV244xA) VIO 300 950 µV VDD = ±2.5 V (5 V); TA = 25°C; VIC = 0, VO = 0, RS = 50 Ω 7
Input offset voltage (TLV244xA) VIO 1600 µV VDD = ±2.5 V (5 V); Full range; VIC = 0, VO = 0, RS = 50 Ω 7
Input offset current IIO 150 pA VDD = 5 V; Full range; VIC = 0, VO = 0, RS = 50 Ω 7
Input bias current IIB 260 pA VDD = 5 V; Full range; VIC = 0, VO = 0, RS = 50 Ω 7
Common-mode input voltage range VICR 0 4 V VDD = 5 V; Full range; /VIO/ ≤ 5 mV, RS = 50 Ω 7
High-level output voltage VOH 4 4.35 V VDD = 5 V; TA = 25°C; IOH = –5 mA 7
High-level output voltage VOH 4 V VDD = 5 V; Full range; IOH = –5 mA 7
Low-level output voltage VOL 1.25 V VDD = 5 V; Full range; VIC = 2.5 V, IOL = 5 mA 7
Large-signal differential voltage amplification AVD 0.9 1.3 V/mV VDD = 5 V; TA = 25°C; RL = 600 Ω (referenced to 2.5 V); VIC = 2.5 V, VO = 1 V to 4 V 7
Large-signal differential voltage amplification AVD 0.5 V/mV VDD = 5 V; Full range; RL = 600 Ω (referenced to 2.5 V); VIC = 2.5 V, VO = 1 V to 4 V 7
Common-mode rejection ratio CMRR 70 75 dB VDD = 5 V; TA = 25°C; VIC = VICR MIN, VO = VDD/2, RS = 50 Ω 7
Common-mode rejection ratio CMRR 70 dB VDD = 5 V; Full range; VIC = VICR MIN, VO = VDD/2, RS = 50 Ω 7
Supply-voltage rejection ratio (ΔVDD/ΔVIO) kSVR 80 95 dB VDD = 5 V; TA = 25°C; VDD = 4.4 V to 8 V, VIC = VDD/2, No load 7
Supply-voltage rejection ratio (ΔVDD/ΔVIO) kSVR 80 dB VDD = 5 V; Full range; VDD = 4.4 V to 8 V, VIC = VDD/2, No load 7
Supply current (per channel) IDD 750 1100 µA VDD = 5 V; TA = 25°C; VO = 2.5 V, No load 7
Supply current (per channel) IDD 1100 µA VDD = 5 V; Full range; VO = 2.5 V, No load 7
Slew rate at unity gain SR 0.75 1.4 V/µs VDD = 5 V; TA = 25°C; VO = 0.5 V to 2.5 V, RL = 600 Ω, CL = 100 pF 8
Slew rate at unity gain SR 0.5 V/µs VDD = 5 V; Full range; VO = 0.5 V to 2.5 V, RL = 600 Ω, CL = 100 pF 8
Supply voltage VDD 2.7 10 V 4
Operating free-air temperature TA -40 125 °C 4
Supply voltage VDD 12 V All voltages referenced to midpoint of VDD+ and VDD– 4
Input voltage (any input) VI -0.3 V Printed as –0.3 V to VDD 4
Input current (any input) II -5 5 mA 4
Output current IO -50 50 mA 4
Total current into VDD+ -50 50 mA 4
Total current out of VDD– -50 50 mA 4
Operating free-air temperature range (absolute maximum) TA -40 125 °C 4
Storage temperature range Tstg -65 150 °C 4
Lead temperature 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 4
Power rating, D (8 pin) package 725 mW TA ≤ 25°C 4
Derating factor, D (8 pin) package 5.8 mW/°C Above TA = 25°C 4
Power rating, D (8 pin) package 145 mW TA = 125°C 4

CAD (KiCad official)

  • Symbol: TLV2442AQDRQ1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tlv2442aqdrq1-etched.step / tlv2442aqdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv2442aqdrq1.step / tlv2442aqdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 8e09f044ccc7a11a, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF