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TLV2432AIPWR

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Texas Instruments Operational Amplifier, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLV2432AIPWR

Texas Instruments · Operational Amplifier · TSSOP-8

TLV2432AIPWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Channel 1 rail-to-rail output, able to drive 600 Ω loads.
2 1IN− input Channel 1 inverting input, with input voltage range from VDD- to VDD+ − 0.8 V per recommended conditions.
3 1IN+ input Channel 1 non-inverting input, with common-mode range from VDD- to VDD+ − 1.3 V per recommended conditions.
4 VDD−/GND power_in Negative supply rail or ground; supply voltage between VDD+ and VDD- is 2.7 V to 10 V.
5 2IN+ input Channel 2 non-inverting input, with common-mode range from VDD- to VDD+ − 1.3 V per recommended conditions.
6 2IN− input Channel 2 inverting input, with input voltage range from VDD- to VDD+ − 0.8 V per recommended conditions.
7 2OUT output Channel 2 rail-to-rail output, able to drive 600 Ω loads.
8 VDD+ power_in Positive supply rail; supply voltage is 2.7 V to 10 V recommended, with 12 V absolute maximum.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD (absolute maximum) VDD 12 V 3
Input voltage range, any input VI -0.3 V any input 3
Input current II -5 5 mA 3
Output current IO -50 50 mA 3
Total current into VDD+ -50 50 mA 3
Total current out of VDD- -50 50 mA 3
Operating free-air temperature TA TA -40 85 °C I suffix (dual), natural air 3
Storage temperature Tstg -65 150 °C 3
Supply voltage VDD (recommended) VDD 2.7 10 V I suffix (dual) 3
Operating free-air temperature TA (recommended) TA -40 85 °C I suffix (dual), natural air 3
Power rating, PW (8) package 525 mW TA ≤ 25°C 3
Power rating, PW (8) package 336 mW TA = 70°C 3
Power rating, PW (8) package 273 mW TA = 85°C 3
Power rating, PW (8) package 105 mW TA = 125°C 3
Input offset voltage (A variant, 25°C) VIO 300 950 µV VDD = 3V; VIC = 0V, VO = 0V, RS = 50Ω, VDD± = ±1.5V; TA = 25°C 4
Input offset voltage (A variant, full range) VIO 1500 µV VDD = 3V; VIC = 0V, VO = 0V, RS = 50Ω, VDD± = ±1.5V; TA = full range 4
Input offset current IIO 0.5 60 pA VDD = 3V; TA = 25°C 4
Input offset current IIO 150 pA VDD = 3V; TA = full range 4
Input bias current IIB 1 60 pA VDD = 3V; TA = 25°C 4
Input bias current IIB 150 pA VDD = 3V; TA = full range 4
Common-mode input voltage range VICR -0.25 2.75 V VDD = 3V; /VIO/ ≤ 5mV, RS = 50Ω; TA = 25°C 4
Common-mode input voltage range VICR 0 2.2 V VDD = 3V; /VIO/ ≤ 5mV, RS = 50Ω; TA = full range 4
High-level output voltage VOH 2.25 V VDD = 3V; IOH = -3mA; TA = full range 4
Low-level output voltage VOL 1 V VDD = 3V; VIC = 1.5V, IOL = 3mA; TA = full range 4
Large-signal differential voltage amplification AVD 1.5 2.5 V/mV VDD = 3V; VIC = 2.5V, VO = 1V to 2V, RL = 2kΩ; TA = 25°C 4
Large-signal differential voltage amplification AVD 1 V/mV VDD = 3V; VIC = 2.5V, VO = 1V to 2V, RL = 2kΩ; TA = full range 4
Large-signal differential voltage amplification AVD 750 V/mV VDD = 3V; VIC = 2.5V, VO = 1V to 2V, RL = 1MΩ; TA = full range 4
Common-mode rejection ratio CMRR 63 83 dB VDD = 3V; VIC = 0V to 2.5V, VO = 1.5V, RS = 50Ω; TA = 25°C 4
Common-mode rejection ratio CMRR 63 dB VDD = 3V; VIC = 0V to 2.5V, VO = 1.5V, RS = 50Ω; TA = full range 4
Supply voltage rejection ratio (ΔVDD/ΔVIO) kSVR 80 95 dB VDD = 2.7V to 8V; VIC = VDD/2, no load; TA = 25°C 4
Supply voltage rejection ratio (ΔVDD/ΔVIO) kSVR 80 dB VDD = 2.7V to 8V; VIC = VDD/2, no load; TA = full range 4
Supply current per channel IDD 115 150 µA VDD = 3V; VO = 1.5V, no load; TA = 25°C 4
Supply current per channel IDD 175 µA VDD = 3V; VO = 1.5V, no load; TA = full range 4
Slew rate at unity gain SR 0.15 0.25 V/µs VDD = 3V; VO = 1V to 2V, RL = 2kΩ, CL = 100pF; TA = 25°C 5
Slew rate at unity gain SR 0.1 V/µs VDD = 3V; VO = 1V to 2V, RL = 2kΩ, CL = 100pF; TA = full range 5
Input offset voltage (A variant, 25°C) VIO 300 950 µV VDD = 5V; VIC = 0V, VO = 0V, RS = 50Ω, VDD± = ±2.5V; TA = 25°C 8
Input offset voltage (A variant, full range) VIO 1500 µV VDD = 5V; VIC = 0V, VO = 0V, RS = 50Ω, VDD± = ±2.5V; TA = full range 8
Input offset current IIO 0.5 60 pA VDD = 5V; TA = 25°C 8
Input offset current IIO 150 pA VDD = 5V; TA = full range 8
Input bias current IIB 1 60 pA VDD = 5V; TA = 25°C 8
Input bias current IIB 150 pA VDD = 5V; TA = full range 8
Common-mode input voltage range VICR -0.25 4.75 V VDD = 5V; /VIO/ ≤ 5mV, RS = 50Ω; TA = 25°C 8
Common-mode input voltage range VICR 0 4.2 V VDD = 5V; /VIO/ ≤ 5mV, RS = 50Ω; TA = full range 8
High-level output voltage VOH 4 4.35 V VDD = 5V; IOH = -5mA; TA = 25°C 8
High-level output voltage VOH 4 V VDD = 5V; IOH = -5mA; TA = full range 8
Low-level output voltage VOL 1.25 V VDD = 5V; VIC = 2.5V, IOL = 5mA; TA = full range 8
Large-signal differential voltage amplification AVD 2.5 3.8 V/mV VDD = 5V; VIC = 2.5V, VO = 1V to 4V, RL = 2kΩ; TA = 25°C 8
Large-signal differential voltage amplification AVD 1.5 V/mV VDD = 5V; VIC = 2.5V, VO = 1V to 4V, RL = 2kΩ; TA = full range 8
Large-signal differential voltage amplification AVD 950 V/mV VDD = 5V; VIC = 2.5V, VO = 1V to 4V, RL = 1MΩ; TA = full range 8
Common-mode rejection ratio CMRR 63 90 dB VDD = 5V; VIC = 0V to 4.5V, VO = 2.5V, RS = 50Ω; TA = 25°C 8
Common-mode rejection ratio CMRR 63 dB VDD = 5V; VIC = 0V to 4.5V, VO = 2.5V, RS = 50Ω; TA = full range 8
Supply voltage rejection ratio (ΔVDD/ΔVIO) kSVR 80 95 dB VDD = 4.4V to 8V; VIC = VDD/2, no load; TA = 25°C 8
Supply voltage rejection ratio (ΔVDD/ΔVIO) kSVR 80 dB VDD = 4.4V to 8V; VIC = VDD/2, no load; TA = full range 8
Supply current per channel IDD 115 150 µA VDD = 5V; VO = 2.5V, no load; TA = 25°C 8
Supply current per channel IDD 175 µA VDD = 5V; VO = 2.5V, no load; TA = full range 8
Slew rate at unity gain SR 0.15 0.25 V/µs VDD = 5V; VO = 1.5V to 3V, RL = 2kΩ, CL = 100pF; TA = 25°C 9
Slew rate at unity gain SR 0.1 V/µs VDD = 5V; VO = 1.5V to 3V, RL = 2kΩ, CL = 100pF; TA = full range 9

CAD (KiCad official)

  • Symbol: TLV2432AIPWR
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: tlv2432aipwr-etched.step / tlv2432aipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv2432aipwr.step / tlv2432aipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 8a7fdd364dfff008, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF