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TLV2362IDGKR

Texas Instruments · Operational Amplifier · VSSOP-8

TLV2362IDGKR from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Output of amplifier 1; the output swings to about ±2.4 V typical at VCC± = ±2.5 V with RL = 10 kΩ and must stay within the absolute maximum output voltage of ±3.5 V.
2 1IN− input Inverting input of amplifier 1; input voltages must not exceed VCC (absolute maximum rating).
3 1IN+ input Non-inverting input of amplifier 1; input voltages must not exceed VCC (absolute maximum rating).
4 VCC− power_in Negative supply rail; recommended supply is ±1 V minimum to ±2.5 V maximum, and the absolute maximum VCC− is −3.5 V.
5 2IN+ input Non-inverting input of amplifier 2; input voltages must not exceed VCC (absolute maximum rating).
6 2IN− input Inverting input of amplifier 2; input voltages must not exceed VCC (absolute maximum rating).
7 2OUT output Output of amplifier 2; the output swings to about ±2.4 V typical at VCC± = ±2.5 V with RL = 10 kΩ and must stay within the absolute maximum output voltage of ±3.5 V.
8 VCC+ power_in Positive supply rail; recommended supply is ±1 V minimum to ±2.5 V maximum, and the absolute maximum VCC+ is 3.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VIO 1 6 mV VCC±=±2.5 V, VO=0, VIC=0, 25°C 5
Input offset voltage VIO 7.5 mV VCC±=±2.5 V, VO=0, VIC=0, full range 5
Input offset voltage VIO 1 6 mV VCC±=±1.5 V, VO=0, VIC=0, 25°C 4
Input offset voltage VIO 7.5 mV VCC±=±1.5 V, VO=0, VIC=0, full range 4
Input offset current IIO 5 100 nA VCC±=±2.5 V, VO=0, VIC=0, 25°C 5
Input offset current IIO 150 nA VCC±=±2.5 V, VO=0, VIC=0, full range 5
Input offset current IIO 5 100 nA VCC±=±1.5 V, VO=0, VIC=0, 25°C 4
Input offset current IIO 150 nA VCC±=±1.5 V, VO=0, VIC=0, full range 4
Input bias current IIB 20 150 nA VCC±=±2.5 V, VO=0, VIC=0, 25°C 5
Input bias current IIB 250 nA VCC±=±2.5 V, VO=0, VIC=0, full range 5
Input bias current IIB 20 150 nA VCC±=±1.5 V, VO=0, VIC=0, 25°C 4
Input bias current IIB 250 nA VCC±=±1.5 V, VO=0, VIC=0, full range 4
Common-mode input voltage VIC -1.5 1.5 V VCC±=±2.5 V, /VIO/ ≤ 7.5 mV, 25°C 5
Common-mode input voltage VIC -1.4 1.4 V VCC±=±2.5 V, /VIO/ ≤ 7.5 mV, full range 5
Common-mode input voltage VIC -0.5 0.5 V VCC±=±1.5 V, /VIO/ ≤ 7.5 mV, 25°C 4
Maximum positive peak output voltage VOM+ 2 2.4 V VCC±=±2.5 V, RL=10 kΩ, 25°C 5
Maximum positive peak output voltage VOM+ 2 V VCC±=±2.5 V, RL≥10 kΩ, full range 5
Maximum positive peak output voltage VOM+ 1.2 1.4 V VCC±=±1.5 V, RL=10 kΩ, 25°C 4
Maximum positive peak output voltage VOM+ 1.2 V VCC±=±1.5 V, RL≥10 kΩ, full range 4
Maximum negative peak output voltage VOM− -2.4 -2 V VCC±=±2.5 V, RL=10 kΩ, 25°C 5
Maximum negative peak output voltage VOM− -2 V VCC±=±2.5 V, RL≥10 kΩ, full range 5
Maximum negative peak output voltage VOM− -1.4 -1.2 V VCC±=±1.5 V, RL=10 kΩ, 25°C 4
Maximum negative peak output voltage VOM− -1.2 V VCC±=±1.5 V, RL≥10 kΩ, full range 4
Supply current (per amplifier) ICC 1.75 2.5 mA VCC±=±2.5 V, VO=0, no load, 25°C 5
Supply current (per amplifier) ICC 3 mA VCC±=±2.5 V, VO=0, no load, full range 5
Supply current (per amplifier) ICC 1.4 2.25 mA VCC±=±1.5 V, VO=0, no load, 25°C 4
Supply current (per amplifier) ICC 2.75 mA VCC±=±1.5 V, VO=0, no load, full range 4
Large-signal differential voltage amplification (TLV2362) AVD 60 dB VCC±=±2.5 V, VO=±1 V, RL=10 kΩ, 25°C 5
Large-signal differential voltage amplification (TLV2362) AVD 55 dB VCC±=±1.5 V, VO=±1 V, RL=10 kΩ, 25°C 4
Common-mode rejection ratio CMRR 85 dB VCC±=±2.5 V, VIC=±0.5 V, 25°C 5
Common-mode rejection ratio CMRR 75 dB VCC±=±1.5 V, VIC=±0.5 V, 25°C 4
Supply-voltage rejection ratio kSVR 80 dB VCC±=±1.5 V to ±2.5 V, 25°C 5
Supply-voltage rejection ratio kSVR 80 dB VCC±=±1.5 V to ±2.5 V, 25°C 4
Supply voltage, VCC+ VCC+ 3.5 V Referenced to midpoint of VCC+ and VCC− 3
Supply voltage, VCC− VCC− -3.5 V Referenced to midpoint of VCC+ and VCC− 3
Differential input voltage VID -3.5 3.5 V IN+ with respect to IN− 3
Output voltage VO -3.5 3.5 V 3
Output current IO 20 mA 3
Operating virtual junction temperature TJ 150 °C 3
Lead temperature 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 3
Storage temperature range Tstg -65 150 °C 3
Supply voltage VCC± 1 2.5 V Supply voltage, each supply 3
Operating free-air temperature (TLV2362I) TA -40 85 °C TLV2362I 3
Package thermal impedance, DGK package θJA 172 °C/W DGK package, JESD 51-7 (see Notes 4 and 5) 3

CAD (KiCad official)

  • Symbol: TLV2362IDGKR
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: tlv2362idgkr-etched.step / tlv2362idgkr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv2362idgkr.step / tlv2362idgkr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 279a60e119e0c604, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF