Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

TLV2264AQD

Texas Instruments · Operational Amplifier · SOIC-14

TLV2264AQD from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Output of amplifier 1 with rail-to-rail swing.
2 1IN− input Inverting input of amplifier 1.
3 1IN+ input Noninverting input of amplifier 1.
4 VDD+ power_in Positive supply, shared by all four amplifiers (2.7 V to 8 V total supply range).
5 2IN+ input Noninverting input of amplifier 2.
6 2IN− input Inverting input of amplifier 2.
7 2OUT output Output of amplifier 2 with rail-to-rail swing.
8 3OUT output Output of amplifier 3 with rail-to-rail swing.
9 3IN− input Inverting input of amplifier 3.
10 3IN+ input Noninverting input of amplifier 3.
11 VDD−/GND power_in Negative supply or ground, shared by all four amplifiers; the common-mode input range includes this rail.
12 4IN+ input Noninverting input of amplifier 4.
13 4IN− input Inverting input of amplifier 4.
14 4OUT output Output of amplifier 4 with rail-to-rail swing.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Amplifiers/Comparators
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VIO 300 950 µV VDD = 3 V; TA = 25°C 18
Input offset voltage (full range) VIO 1500 µV VDD = 3 V; full range (−40°C to 125°C) 18
Input offset current IIO 0.5 60 pA VDD = 3 V; VIC = 0, VO = 0, RS = 50 Ω; TA = 25°C 18
Input offset current (125°C) IIO 800 pA VDD = 3 V; VIC = 0, VO = 0, RS = 50 Ω; TA = 125°C 18
Input bias current IIB 1 60 pA VDD = 3 V; TA = 25°C 18
Input bias current (125°C) IIB 800 pA VDD = 3 V; TA = 125°C 18
Common-mode input voltage range VICR -0.3 2.2 V VDD = 3 V; RS = 50 Ω, /VIO/ ≤ 5 mV; TA = 25°C 18
Common-mode input voltage range (full range) VICR 0 1.7 V VDD = 3 V; RS = 50 Ω, /VIO/ ≤ 5 mV; full range 18
High-level output voltage VOH 2.99 V VDD = 3 V; IOH = −20 µA; TA = 25°C 18
High-level output voltage VOH 2.85 V VDD = 3 V; IOH = −100 µA; TA = 25°C 18
High-level output voltage (full range) VOH 2.82 V VDD = 3 V; IOH = −100 µA; full range 18
High-level output voltage VOH 2.7 V VDD = 3 V; IOH = −400 µA; TA = 25°C 18
High-level output voltage (full range) VOH 2.6 V VDD = 3 V; IOH = −400 µA; full range 18
Low-level output voltage VOL 10 mV VDD = 3 V; VIC = 1.5 V, IOL = 50 µA; TA = 25°C 18
Low-level output voltage VOL 100 150 mV VDD = 3 V; VIC = 1.5 V, IOL = 500 µA; TA = 25°C 18
Large-signal differential voltage amplification AVD 60 100 V/mV VDD = 3 V; VIC = 1.5 V, VO = 1 V to 2 V, RL = 50 kΩ; TA = 25°C 18
Large-signal differential voltage amplification (full range) AVD 25 V/mV VDD = 3 V; VIC = 1.5 V, VO = 1 V to 2 V, RL = 50 kΩ; full range 18
Common-mode rejection ratio CMRR 65 77 dB VDD = 3 V; VIC = 0 to 1.7 V, VO = 1.5 V, RS = 50 Ω; TA = 25°C 18
Common-mode rejection ratio (full range) CMRR 60 dB VDD = 3 V; VIC = 0 to 1.7 V, VO = 1.5 V, RS = 50 Ω; full range 18
Supply voltage rejection ratio kSVR 80 100 dB VDD = 2.7 V to 8 V; TA = 25°C 18
Supply voltage rejection ratio (full range) kSVR 80 dB VDD = 2.7 V to 8 V, VIC = VDD/2, no load; full range 18
Supply current (four amplifiers) IDD 0.8 1 mA VDD = 3 V; VO = 1.5 V, no load; TA = 25°C 19
Supply current (four amplifiers, full range) IDD 1 mA VDD = 3 V; VO = 1.5 V, no load; full range 19
Slew rate at unity gain SR 0.35 0.55 V/µs VDD = 3 V; VO = 0.5 V to 1.7 V, RL = 50 kΩ; TA = 25°C 19
Slew rate at unity gain (full range) SR 0.25 V/µs VDD = 3 V; VO = 0.5 V to 1.7 V, CL = 100 pF, RL = 50 kΩ; full range 19
Input offset voltage VIO 300 950 µV VDD = 5 V; TA = 25°C 20
Input offset voltage (full range) VIO 1500 µV VDD = 5 V; full range (−40°C to 125°C) 20
Input offset current IIO 0.5 60 pA VDD = 5 V; VIC = 0, VO = 0, RS = 50 Ω; TA = 25°C 20
Input offset current (125°C) IIO 800 pA VDD = 5 V; VIC = 0, VO = 0, RS = 50 Ω; TA = 125°C 20
Input bias current IIB 1 60 pA VDD = 5 V; TA = 25°C 20
Input bias current (125°C) IIB 800 pA VDD = 5 V; TA = 125°C 20
Common-mode input voltage range VICR -0.3 4.2 V VDD = 5 V; /VIO/ ≤ 5 mV, RS = 50 Ω; TA = 25°C 20
Common-mode input voltage range (full range) VICR 0 3.5 V VDD = 5 V; /VIO/ ≤ 5 mV, RS = 50 Ω; full range 20
High-level output voltage VOH 4.99 V VDD = 5 V; IOH = −20 µA; TA = 25°C 20
High-level output voltage VOH 4.85 4.94 V VDD = 5 V; IOH = −100 µA; TA = 25°C 20
High-level output voltage (full range) VOH 4.82 V VDD = 5 V; IOH = −100 µA; full range 20
High-level output voltage VOH 4.7 4.85 V VDD = 5 V; IOH = −400 µA; TA = 25°C 20
High-level output voltage (full range) VOH 4.5 V VDD = 5 V; IOH = −400 µA; full range 20
Low-level output voltage VOL 0.01 V VDD = 5 V; VIC = 2.5 V, IOL = 50 µA; TA = 25°C 20
Low-level output voltage VOL 0.09 0.15 V VDD = 5 V; VIC = 2.5 V, IOL = 500 µA; TA = 25°C 20
Low-level output voltage (full range) VOL 0.15 V VDD = 5 V; VIC = 2.5 V, IOL = 500 µA; full range 20
Large-signal differential voltage amplification AVD 80 170 V/mV VDD = 5 V; VIC = 2.5 V, VO = 1 V to 4 V, RL = 50 kΩ; TA = 25°C 20
Large-signal differential voltage amplification (full range) AVD 50 V/mV VDD = 5 V; VIC = 2.5 V, VO = 1 V to 4 V, RL = 50 kΩ; full range 20
Common-mode rejection ratio CMRR 70 83 dB VDD = 5 V; VIC = 0 to 2.7 V, VO = 2.5 V, RS = 50 Ω; TA = 25°C 20
Common-mode rejection ratio (full range) CMRR 70 dB VDD = 5 V; VIC = 0 to 2.7 V, VO = 2.5 V, RS = 50 Ω; full range 20
Supply voltage rejection ratio kSVR 80 95 dB VDD = 4.4 V to 8 V, VIC = VDD/2, no load; TA = 25°C 20
Supply voltage rejection ratio (full range) kSVR 80 dB VDD = 4.4 V to 8 V, VIC = VDD/2, no load; full range 20
Supply current (four amplifiers) IDD 0.8 1 mA VDD = 5 V; VO = 2.5 V, no load; TA = 25°C 21
Supply current (four amplifiers, full range) IDD 1 mA VDD = 5 V; VO = 2.5 V, no load; full range 21
Slew rate at unity gain SR 0.35 0.55 V/µs VDD = 5 V; VO = 0.5 V to 3.5 V, RL = 50 kΩ; TA = 25°C 21
Slew rate at unity gain (full range) SR 0.25 V/µs VDD = 5 V; VO = 0.5 V to 3.5 V, CL = 100 pF, RL = 50 kΩ; full range 21
Supply voltage VDD 2.7 8 V Q suffix 5
Operating free-air temperature TA -40 125 °C Q suffix 5
Supply voltage VDD 16 V 5
Input current (each input) II -5 5 mA each input 5
Output current IO -50 50 mA 5
Total current into VDD+ -50 50 mA 5
Storage temperature range Tstg -65 150 °C 5
Continuous total power dissipation (D-14 package) 950 mW D-14 package, TA ≤ 25°C 5

CAD (KiCad official)

  • Symbol: TLV2264AQD
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: tlv2264aqd-etched.step / tlv2264aqd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv2264aqd.step / tlv2264aqd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (70 pp, sha256 2773bab46edcaf7a, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF