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TLV1922DSGR

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Texas Instruments , WSON-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLV1922DSGR

Texas Instruments · IC · WSON-8

TLV1922DSGR from Texas Instruments, in a WSON-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 V+ power_in Positive supply voltage, 3.3V to 65V operating range (absolute maximum 70V from GND).
2 IN1- input Inverting input of comparator 1, fail-safe up to 65V; its non-inverting input is internally connected to the 2.5V reference.
3 IN2- input Inverting input of comparator 2, fail-safe up to 65V from GND.
4 IN2+ input Non-inverting input of comparator 2, fail-safe up to 65V from GND and can be connected to the reference output or an external reference.
5 REF_OUT output 2.5V reference output that can source or sink up to 1mA and is internally connected to the non-inverting input of comparator 1.
6 OUT2 output Open-drain output of comparator 2, can be pulled up to 65V independent of V+.
7 OUT1 output Open-drain output of comparator 1, can be pulled up to 65V independent of V+.
8 GND power_in Negative supply voltage (ground).
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-8
Category
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VOS -3 0.5 3 mV 7
Input offset voltage over temperature VOS -4 4 mV TA = -40°C to +125°C 7
Input hysteresis voltage VHYS 1.2 3 5 mV 7
Input hysteresis voltage over temperature VHYS 1 6 mV TA = -40°C to +125°C 7
Reference voltage VOUT 2.462 2.5 2.538 V 7
Reference accuracy Accuracy -1.5 0.2 1.5 % 7
Reference accuracy over temperature Accuracy -1.75 1.75 % TA = -40°C to +125°C 7
Reference temperature drift dVOUT/dT 40 100 ppm/℃ TA = -40°C to +125°C 7
Line regulation dVOUT/dVS 10 100 µV/V 3.3V ≤ VS ≤ 65V 7
Input bias current over temperature IB -1.2 1.2 nA TA = -40°C to +125°C 7
Output voltage swing from (V-) VOL 150 300 mV VPU = 5V, RPU = 10k, ISINK = 5mA, TA = -40°C to +125°C 7
Quiescent current per comparator IQ 8 11 µA Output is logic high, VPU = 5V, RPU = 10k 7
Quiescent current per comparator over temperature IQ 13 µA Output is logic high, VPU = 5V, RPU = 10k, TA = -40°C to +125°C 7
Reference output current ILOAD 1 mA 7
Supply voltage VS -0.3 70 V VS = (V+), GND 5
Input pins voltage from GND IN+, IN- -0.3 65 V 5
Current into input pins IN+, IN- -10 10 mA 5
Comparator output voltage from GND OUT -0.3 65 V 5
Comparator output short circuit current 10 mA Short-circuit to +5V 5
Junction temperature TJ 150 °C 5
Storage temperature Tstg -65 150 °C 5
Supply voltage VS 3.3 65 V VS = (V+), GND 6
Input voltage range from GND -0.2 65 V 6
Output voltage range from GND -0.2 65 V 6
Ambient temperature TA -40 125 °C 6
Junction-to-ambient thermal resistance RθJA 78 °C/W DSG (WSON-8) 6
Junction-to-case (top) thermal resistance RθJC(top) 99.8 °C/W DSG (WSON-8) 6
Junction-to-board thermal resistance RθJB 44.4 °C/W DSG (WSON-8) 6
Junction-to-top characterization parameter ψJT 5 °C/W DSG (WSON-8) 6
Junction-to-board characterization parameter ψJB 44.4 °C/W DSG (WSON-8) 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 19.5 °C/W DSG (WSON-8) 6
Input offset voltage drift dVIO/dT 1.2 µV/°C VCM = 2.5V, TA = -40°C to +125°C 7
Input common mode capacitance CIC 2 pF 7
Load regulation, sourcing dVOUT/dILOAD 4 mV/mA 0mA < ISOURCE ≤ 0.5mA 7
Load regulation, sinking dVOUT/dILOAD 4 mV/mA 0mA < ISINK ≤ 0.5mA 7
Reference noise Vnoise 0.2 mVPP f = 0.1Hz to 10Hz 7
Input bias current IB 2 pA 7
Input offset current IOS 20 pA 7
Input differential mode capacitance CID 8 pF 7
Short-circuit current IOL 35 mA Sinking @5V, TA = -40°C to +125°C 7
Power on reset voltage VPOR 2.45 V 8
Power-up time tON 2 ms 8
Propagation delay time, low-to-high TPD-LH 1.2 µs VOD = 100mV, VUD = 100mV CL = 15pF, TA = 25°C, VCM = VREF 8
Propagation delay time, high-to-low TPD-HL 0.9 µs VOD = 100mV, VUD = 100mV CL = 15pF, TA = 25°C, VCM = VREF 8
Output fall time, 80% to 20% TFALL 10 ns CL = 15 pF, VOD = 100mV, VUD = 100mV, RPU = 5.1k 8
ESD, human-body model V(ESD) -2000 2000 V HBM, ANSI/ESDA/JEDEC JS-001 5
ESD, charged-device model V(ESD) -1000 1000 V CDM, ANSI/ESDA/JEDEC JS-002 5

CAD (KiCad official)

  • Symbol: TLV1922DSGR
  • Footprint: Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm
  • 3D model: WSON-8, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tlv1922dsgr-etched.step / tlv1922dsgr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv1922dsgr.step / tlv1922dsgr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 5f807c86193e72f7, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF