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TLP7820

Public Made by Adom

by adom

TOSHIBA Isolation Amplifiers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLP7820

TOSHIBA · Isolation Amplifiers · SOIC-8

TLP7820 from TOSHIBA, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Input side supply voltage, 4.5 to 5.5 V recommended (absolute max -0.5 to 6 V), with a 0.1 µF bypass capacitor between pins 1 and 4.
2 VIN+ power_in Positive analog input, recommended ±200 mV (FSR ±300 mV typ.); keep below VDD1 - 2 V to avoid test modes.
3 VIN- power_in Negative analog input, normally tied to input ground (0 V); keep below VDD1 - 2 V to avoid test modes.
4 GND1 power_in Input side ground, with a 0.1 µF bypass capacitor between pins 1 and 4.
5 GND2 power_in Output side ground, with a 0.1 µF bypass capacitor between pins 5 and 8.
6 VOUT- output Negative output of the differential analog output, with a typical gain of 8.2 V/V relative to VOUT+.
7 VOUT+ output Positive output of the differential analog output, with a typical gain of 8.2 V/V relative to VOUT-.
8 VDD2 power_in Output side supply voltage, 3 to 5.5 V recommended (absolute max -0.5 to 6 V), with a 0.1 µF bypass capacitor between pins 5 and 8.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package SOIC-8
Category Operational Amplifier/Comparator
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD1, VDD2 -0.5 6 V Ta = 25°C 3
Steady-state input voltage VIN+, VIN- -0.5 V -0.5 to VDD1 + 0.5 3
Two-second transient input voltage VIN+, VIN- -6 V -6 to VDD1 + 0.5 3
Input power dissipation PD 72 mW Ta = 25°C 3
Input power dissipation derating ΔPD/ΔTa -5 mW/°C Ta ≥ 110.6°C 3
Output power dissipation PO 60 mW Ta = 25°C 3
Output power dissipation derating ΔPO/ΔTa -5 mW/°C Ta ≥ 113.0°C 3
Operating temperature Topr -40 105 °C 3
Storage temperature Tstg -55 125 °C 3
Lead soldering temperature Tsol 260 °C 10 s 3
Isolation voltage BVS 5000 Vrms AC, 60 s, R.H. ≤ 60 % 3
Input side supply voltage VDD1 4.5 5 5.5 V 3
Output side supply voltage VDD2 3 5.5 V 3
Analog input voltage VIN+, VIN- -200 200 mV 3
Ambient temperature Ta -40 105 °C 3
Input offset voltage VOS -0.6 0.92 2.46 mV Ta = 25°C 4
Gain (None) G3 7.95 8.2 8.44 V/V Ta = 25°C 4
Gain drift vs ambient temperature /dG/dTa/ 0.00012 V/V/°C 4
VOUT non-linearity (±200 mV) NL200 0.02 0.13 % VIN+ = -200 to 200 mV, Ta = 25°C 4
VOUT non-linearity (±100 mV) NL100 0.015 0.06 % VIN+ = -100 to 100 mV, Ta = 25°C 4
VOUT bandwidth (-3 dB) f-3dB 140 230 kHz VIN+ = 400 mVp-p, sine wave 5
Common-mode transient immunity CMTI 15 20 kV/µs VCM = 1 kV, Ta = 25°C 5
Total capacitance (input to output) CS 1 pF VS = 0 V, f = 1 MHz 5
Isolation voltage BVS 5000 Vrms AC, 60 s 5

CAD (KiCad official)

  • Symbol: TLP7820
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tlp7820-etched.step / tlp7820-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlp7820.step / tlp7820.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (15 pp, sha256 ac8a84e613f3fa2a, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF