component
TLP2161
Public Made by Adomby adom
TOSHIBA Logic Output Optoisolators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLP2161
TOSHIBA · Logic Output Optoisolators · SO-8
TLP2161 from TOSHIBA, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Anode1 | passive | Anode of input LED1; LED1 is driven by the input forward current, tested at IF = 2 mA. |
| 2 | Cathode1 | passive | Cathode of input LED1, which is ON in the high-input state of the truth table. |
| 3 | Cathode2 | passive | Cathode of input LED2, which is ON in the low-input state of the truth table. |
| 4 | Anode2 | passive | Anode of input LED2, driven by the input forward current in the same manner as LED1. |
| 5 | GND | power_in | Ground reference for the detector circuit; a 0.1 µF ceramic bypass capacitor must be connected between pin 8 and pin 5, placed within 1 cm of each pin. |
| 6 | VO2 (Output2) | output | Output 2 of the detector, a totem-pole inverter-logic output. |
| 7 | VO1 (Output1) | output | Output 1 of the detector, a totem-pole inverter-logic output. |
| 8 | VCC | power_in | Supply pin, specified for 2.7 V to 5.5 V and requiring a 0.1 µF bypass capacitor to pin 5. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SO-8 |
| Category | Optoisolators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input forward voltage | VF | 1.35 | 1.5 | 1.65 | V | IF = 2 mA, Ta = 25 °C | 4 |
| Input reverse current | IR | 10 | µA | VR = 5 V, Ta = 25 °C | 4 | ||
| High-level output voltage | VOH | 3.2 | 3.29 | V | VF = 0.8 V, IO = -20 µA, VCC = 3.3 V | 4 | |
| High-level output voltage | VOH | 4.9 | 4.99 | V | VF = 0.8 V, IO = -20 µA, VCC = 5.0 V | 4 | |
| High-level output voltage | VOH | 2.3 | 3.15 | V | VF = 0.8 V, IO = -3.2 mA, VCC = 3.3 V | 4 | |
| High-level output voltage | VOH | 4 | 4.87 | V | VF = 0.8 V, IO = -3.2 mA, VCC = 5.0 V | 4 | |
| Low-level output voltage | VOL | 0.1 | V | IF = 2 mA, IO = 20 µA | 4 | ||
| Threshold input current (H/L) | IFHL | 1.3 | mA | IO = 3.2 mA, VO < 0.4 V, Ta = -40 to 105 °C | 4 | ||
| Threshold input current (H/L) | IFHL | 1.6 | mA | IO = 3.2 mA, VO < 0.4 V, Ta = -40 to 125 °C | 4 | ||
| Propagation delay time (H/L) | tpHL | 49 | 80 | ns | IF = 0 → 2 mA, RT = 1.68 kΩ, CL = 15 pF | 5 | |
| High-level common-mode transient immunity | CMH | -20 | 20 | kV/µs | IF = 0 mA, VCC = 3.3 / 5 V, VCM = 1000 Vp-p, RT = 1.68 kΩ, Ta = 25 °C | 5 | |
| Low-level common-mode transient immunity | CML | -20 | 20 | kV/µs | IF = 2 mA, VCC = 3.3 / 5 V, VCM = 1000 Vp-p, RT = 1.68 kΩ, Ta = 25 °C | 5 | |
| Isolation voltage | BVS | 2500 | Vrms | AC, 60 s | 4 | ||
| Input forward current | IF | 10 | mA | Each channel | 3 | ||
| Input forward current (pulsed) | IFP | 40 | mA | Each channel; PW ≤ 1 ms, duty = 50% | 3 | ||
| Input forward current derating | ∆IF/∆Ta | -0.13 | mA/°C | Ta ≥ 110 °C; each channel | 3 | ||
| Input forward current (pulsed) derating | ∆IFP/∆Ta | -1.01 | mA/°C | Ta ≥ 110 °C; each channel | 3 | ||
| Input power dissipation | PD | 20 | mW | Each channel | 3 | ||
| Input power dissipation derating | ∆PD/∆Ta | -0.55 | mW/°C | Ta ≥ 110 °C; each channel | 3 | ||
| Operating temperature | Topr | -40 | 125 | °C | 3 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 3 | ||
| Lead soldering temperature | Tsol | 260 | °C | 10 s | 3 | ||
| Isolation voltage | BVS | 2500 | Vrms | AC, 60 s, R.H. ≤ 60 % | 3 | ||
| Input on-state current | IF(ON) | 6 | mA | Each channel; rise and fall times of input on-current less than 0.5 µs | 3 | ||
| Input off-state voltage | VF(OFF) | 0.8 | V | Each channel | 3 | ||
| Supply voltage | VCC | 2.7 | 5.5 | V | 3 | ||
| Operating temperature | Topr | -40 | 125 | °C | 3 |
CAD (KiCad official)
- Symbol:
TLP2161 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
tlp2161-etched.step/tlp2161-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlp2161.step/tlp2161.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (17 pp, sha256
031b393d2b28bc8e, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).