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TLK1221RHAR

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Texas Instruments Ethernet Transceivers, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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TLK1221RHAR

Texas Instruments · Ethernet Transceivers · VQFN-40-EP(6x6)

TLK1221RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ENABLE input Device enable; when held low, all circuits are disabled for ultralow-power Iddq testing; when held high, device operates normally. Internal pullup resistor.
2 TD0 input Transmit data bit 0; part of 10-bit parallel data input clocked on rising edge of REFCLK.
3 TD1 input Transmit data bit 1; part of 10-bit parallel data input clocked on rising edge of REFCLK.
4 TD2 input Transmit data bit 2; part of 10-bit parallel data input clocked on rising edge of REFCLK.
5 TD3 input Transmit data bit 3; part of 10-bit parallel data input clocked on rising edge of REFCLK.
6 VDD power_in Digital logic power supply for all digital circuitry and digital I/O buffers; 2.3 to 2.7 V nominal 2.5 V.
7 TD4 input Transmit data bit 4; part of 10-bit parallel data input clocked on rising edge of REFCLK.
8 TD5 input Transmit data bit 5; part of 10-bit parallel data input clocked on rising edge of REFCLK.
9 TD6 input Transmit data bit 6; part of 10-bit parallel data input clocked on rising edge of REFCLK.
10 TD7 input Transmit data bit 7; part of 10-bit parallel data input clocked on rising edge of REFCLK.
11 TD8 input Transmit data bit 8; part of 10-bit parallel data input clocked on rising edge of REFCLK.
12 TD9 input Transmit data bit 9; last bit of 10-bit parallel data input clocked on rising edge of REFCLK; transmitted as first bit.
13 RBCMODE input Receive byte clock mode select; when low selects TBI half-rate mode (30-65 MHz on RBC0, RBC1); when high selects TBI full-rate mode (60-130 MHz on RBC0). Internal pulldown resistor.
14 REFCLK input Reference clock input (60 MHz to 130 MHz); synchronizes receiver and transmitter interface; used to register transmit data (TD0-TD9) on rising edge.
15 LOOPEN input Loop enable; when high activates internal loopback path routing transmitted serial data to receiver for self-test; TXP and TXN held high-impedance during loopback. Internal pulldown resistor.
16 VDD power_in Digital logic power supply for all digital circuitry and digital I/O buffers; 2.3 to 2.7 V nominal 2.5 V.
17 RBC0 output Receive byte clock 0; recovered clock for synchronizing 10-bit output data on RD0-RD9; in half-rate mode at one-half data rate, in full-rate mode at 1/10th serial data rate.
18 RBC1 output Receive byte clock 1; recovered clock for synchronizing 10-bit output data on RD0-RD9; in half-rate mode 180 degrees out of phase with RBC0 at one-half data rate; in full-rate mode held low.
19 RD9 output Receive data bit 9; last bit of 10-bit parallel data output from transceiver; referenced to RBC0 and RBC1.
20 RD8 output Receive data bit 8; part of 10-bit parallel data output from transceiver; referenced to RBC0 and RBC1.
21 RD7 output Receive data bit 7; part of 10-bit parallel data output from transceiver; referenced to RBC0 and RBC1.
22 RD6 output Receive data bit 6; part of 10-bit parallel data output from transceiver; referenced to RBC0 and RBC1.
23 RD5 output Receive data bit 5; part of 10-bit parallel data output from transceiver; referenced to RBC0 and RBC1.
24 RD4 output Receive data bit 4; part of 10-bit parallel data output from transceiver; referenced to RBC0 and RBC1.
25 RD3 output Receive data bit 3; part of 10-bit parallel data output from transceiver; referenced to RBC0 and RBC1.
26 VDD power_in Digital logic power supply for all digital circuitry and digital I/O buffers; 2.3 to 2.7 V nominal 2.5 V.
27 RD2 output Receive data bit 2; part of 10-bit parallel data output from transceiver; referenced to RBC0 and RBC1.
28 RD1 output Receive data bit 1; part of 10-bit parallel data output from transceiver; referenced to RBC0 and RBC1.
29 RD0 output Receive data bit 0; first bit received; part of 10-bit parallel data output from transceiver to protocol layer; referenced to RBC0 and RBC1.
30 SYNC/PASS output Synchronous detect output asserted high upon detection of K28.5 comma pattern when SYNCEN is high; in PRBS test mode (PRBSEN = high) outputs PRBS test results (high = pass).
31 PRBSEN input PRBS enable; when high enables PRBS generation on transmit side and PRBS verification on receive side; allows bit-error-rate testing of serial data. Internal pulldown resistor.
32 SYNCEN input Synchronous function enable; when high activates internal synchronization function detecting K28.5 comma pattern (0011 1110 10) and realigning data on byte boundaries if required; when low disables framing. Internal pullup resistor.
33 RXN input Differential serial input receive negative; part of PECL-compatible differential receiver input interface from copper or optical interface module; minimum differential input voltage 200 mV.
34 RXP input Differential serial input receive positive; part of PECL-compatible differential receiver input interface from copper or optical interface module; receiver common mode voltage 1.0 to 2.25 V.
35 GNDA power_in Analog ground; provides ground reference for high-speed analog circuits, receiver, and transmitter.
36 VDDPLL power_in PLL power supply; provides power for PLL circuitry; requires additional filtering capacitance of 0.01 µF; voltage 2.3 to 2.7 V nominal 2.5 V.
37 VDDA power_in Analog power supply; provides power for high-speed analog circuits, receiver, and transmitter; voltage 2.3 to 2.7 V nominal 2.5 V.
38 TXP output Differential serial output transmit positive; PECL-compatible differential output to copper or optical interface module; 600 to 1100 mV output voltage with 50 Ω termination; held high-impedance when LOOPEN is high.
39 TXN output Differential serial output transmit negative; PECL-compatible differential output to copper or optical interface module; held high-impedance when LOOPEN is high.
40 GNDA power_in Analog ground; provides ground reference for high-speed analog circuits, receiver, and transmitter.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Interface
Pins 41

CAD (KiCad official)

  • Symbol: TLK1221RHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: tlk1221rhar-etched.step / tlk1221rhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlk1221rhar.step / tlk1221rhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 77f33e3761f86a29, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF