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TLK110PT
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Texas Instruments Ethernet Transceivers, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# TLK110PT++**Texas Instruments** · Ethernet Transceivers · LQFP-48(7x7)++TLK110PT from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TX_CLK | output | MII transmit clock providing a 25MHz or 2.5MHz reference depending on speed; unused in RMII mode. |+| 2 | TX_EN | input | Transmit enable, presented on the rising edge of TX_CLK and active high, indicating valid data on TXD[3:0] in MII mode or TXD[1:0] in RMII mode. |+| 3 | TXD_0 | input | Transmit data bit 0 from the MAC, synchronous to TX_CLK in MII mode or to the 50MHz reference on XI in RMII mode. |+| 4 | TXD_1 | input | Transmit data bit 1 from the MAC, synchronous to TX_CLK in MII mode or to the 50MHz reference on XI in RMII mode. |+| 5 | TXD_2 | input | Transmit data bit 2 from the MAC, synchronous to TX_CLK in MII mode (not used in RMII mode, which uses TXD[1:0]). |+| 6 | TXD_3 | input | Transmit data bit 3 from the MAC, synchronous to the rising edge of TX_CLK in MII mode (not used in RMII mode). |+| 7 | INT/PWDN | bidirectional | Active-low power-down input by default, or open-drain interrupt output when enabled through register access, with a weak internal pull-up that may need an external pull-up. |+| 8 | JTAG_TCK | input | JTAG test clock input with a weak internal pullup. |+| 9 | JTAG_TDO | output | JTAG test data output. |+| 10 | JTAG_TMS | input | JTAG test mode select input with a weak internal pullup. |+| 11 | JTAG_TRST | input | Active-low asynchronous JTAG test reset input with a weak internal pullup. |+| 12 | JTAG_TDI | input | JTAG test data input with a weak internal pullup. |+| 13 | RD- | bidirectional | Differential receive input pair auto-configured for 100Base-TX or 10Base-T; requires 3.3V bias and serves as the transmit output pair in Auto-MDIX crossover. |+| 14 | RD+ | bidirectional | Differential receive input pair auto-configured for 100Base-TX or 10Base-T; requires 3.3V bias and serves as the transmit output pair in Auto-MDIX crossover. |+| 15 | AGND | power_in | Analog ground. |+| 16 | TD- | bidirectional | Differential transmit output pair automatically configured for 10Base-T or 100Base-TX; requires 3.3V bias and serves as the receive input pair in Auto-MDIX mode. |+| 17 | TD+ | bidirectional | Differential transmit output pair automatically configured for 10Base-T or 100Base-TX; requires 3.3V bias and serves as the receive input pair in Auto-MDIX mode. |+| 18 | PFBIN1 | input | Power feedback input fed from PFBOUT in single-supply operation, or connected to a 1.55V external supply in multiple-supply operation, with a 0.1µF capacitor close to the pin. |+| 19 | AGND | power_in | Analog ground. |+| 20 | RESERVED | bidirectional | Reserved pin that must be pulled up to AVDD33 through a 2.2kΩ resistor. |+| 21 | SW_STRAP | input | Connecting an external pull-up resistor to this pin disables software strapping mode during power-up or hardware reset. |+| 22 | AVDD33 | power_in | Analog 3.3V power supply. |+| 23 | PFBOUT | power_out | Power feedback output for the internal regulator; place 10µF and 0.1µF ceramic capacitors close to the pin and connect to PFBIN1 and PFBIN2 in single-supply operation, otherwise not used. |+| 24 | RBIAS | input | Bias resistor connection; use a 4.87kΩ 1% resistor from RBIAS to GND. |+| 25 | CLKOUT | output | Clock output providing 25MHz in MII mode or 50MHz in RMII mode for use by other devices. |+| 26 | LED_ACT/COL/AN_EN | bidirectional | Configurable LED pin indicating activity (mode 1), collision (mode 2) or duplex (mode 3), which also serves as the AN_EN configuration strap. |+| 27 | LED_SPEED/AN_1 | bidirectional | Speed LED that is ON at 100Mb/s and OFF at 10Mb/s, which also serves as the AN_1 configuration strap. |+| 28 | LED_LINK/AN_0 | bidirectional | Link status LED that is ON for a good link, which also serves as the AN_0 configuration strap. |+| 29 | RESET | input | Active-low reset input that reinitializes all internal registers when asserted low for at least 1µs. |+| 30 | MDIO | bidirectional | Bidirectional management data signal synchronized to MDC that requires a 2.2kΩ pull-up resistor. |+| 31 | MDC | input | Management data clock with a maximum rate of 25MHz and no minimum rate, not required to be synchronous to TX_CLK or RX_CLK. |+| 32 | VDD_IO | power_in | I/O supply of 3.3V, 2.5V, or 1.8V (1.8V for MII mode only). |+| 33 | XO | output | Crystal output used only with a crystal; left floating when an oscillator drives XI. |+| 34 | XI | input | Reference clock input: 25MHz ±50ppm crystal or CMOS oscillator in MII mode, or 50MHz ±50ppm CMOS oscillator in RMII mode. |+| 35 | IOGND | power_in | I/O ground. |+| 36 | DGND | power_in | Digital ground. |+| 37 | PFBIN2 | input | Power feedback input fed from PFBOUT in single-supply operation, or connected to a 1.55V external supply in multiple-supply operation, with a 0.1µF capacitor close to the pin. |+| 38 | RX_CLK | output | MII receive clock providing a 25MHz or 2.5MHz reference derived from the received data stream, depending on speed. |+| 39 | RX_DV/MII_MODE | bidirectional | Receive data valid indicating valid data on RXD[3:0] (MII) or RXD[1:0] (RMII) independent of carrier sense, with this pin also sampled as the MII_MODE configuration strap. |+| 40 | CRS/CRS_DV/LED_CFG | bidirectional | Carrier sense asserted high when the receive medium is non-idle in MII mode, or the combined CRS_DV indication in RMII mode, with this pin also serving as the LED_CFG strap. |+| 41 | RX_ER/AMDIX_EN | bidirectional | Receive error indication asserted on an error symbol in MII or RMII mode, with this pin also serving as the AMDIX_EN configuration strap. |+| 42 | COL/PHYAD0 | bidirectional | Collision detect that is always low in MII full-duplex mode and unused in RMII mode, with this pin also serving as the PHYAD0 address bit (LSB, pulled up). |+| 43 | RXD_0/PHYAD1 | bidirectional | Receive data bit 0 synchronous to RX_CLK in MII mode or two-bit RXD[1:0] in RMII mode, also serving as PHY address bit PHYAD1 (pulled down). |+| 44 | RXD_1/PHYAD2 | bidirectional | Receive data bit 1 synchronous to RX_CLK, also serving as PHY address bit PHYAD2 (pulled down). |+| 45 | RXD_2/PHYAD3 | bidirectional | Receive data bit 2 synchronous to RX_CLK, also serving as PHY address bit PHYAD3 (pulled down). |+| 46 | RXD_3/PHYAD4 | bidirectional | Receive data bit 3 synchronous to RX_CLK, also serving as PHY address bit PHYAD4 (pulled down). |+| 47 | IOGND | power_in | I/O ground. |+| 48 | VDD_IO | power_in | I/O supply of 3.3V, 2.5V, or 1.8V (1.8V for MII mode only). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-48(7x7) |+| Category | Interface |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `TLK110PT`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `tlk110pt-etched.step` / `tlk110pt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlk110pt.step` / `tlk110pt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlk110) (104 pp, sha256 `deab430dfd9c08b2`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlk110pt-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "tlk110pt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tlk110pt.kicad_sym",+ "tlk110pt.kicad_mod",+ "tlk110pt.glb",+ "tlk110pt.step",+ "tlk110pt.lbr",+ "docs/hero.png",+ "docs/tlk110pt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tlk110pt-hero.glb",+ "tlk110pt-hero.overlay.json"+ ],+ "component": {+ "mpn": "TLK110PT",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tlk110",+ "parts": {+ "symbol": "tlk110pt.kicad_sym",+ "footprint": "tlk110pt.kicad_mod",+ "model_3d": "tlk110pt-hero.glb",+ "model_3d_plain": "tlk110pt.glb",+ "model_3d_step": "tlk110pt-etched.step",+ "model_3d_step_plain": "tlk110pt.step",+ "lbr": "tlk110pt.lbr"+ },+ "distributor_links": {+ "lcsc": "C181659",+ "digikey": "296-30163-ND",+ "mouser": "595-TLK110PT"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T06:34:50Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-30163-ND",+ "status": "found",+ "lifecycle": "Not For New Designs"+ },+ "mouser": {+ "pn": "595-TLK110PT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "TX_CLK",+ "type": "output",+ "description": "MII transmit clock providing a 25MHz or 2.5MHz reference depending on speed; unused in RMII mode."+ },+ {+ "number": "2",+ "name": "TX_EN",+ "type": "input",+ "description": "Transmit enable, presented on the rising edge of TX_CLK and active high, indicating valid data on TXD[3:0] in MII mode or TXD[1:0] in RMII mode."+ },+ {+ "number": "3",+ "name": "TXD_0",+ "type": "input",+ "description": "Transmit data bit 0 from the MAC, synchronous to TX_CLK in MII mode or to the 50MHz reference on XI in RMII mode."+ },+ {+ "number": "4",+ "name": "TXD_1",+ "type": "input",+ "description": "Transmit data bit 1 from the MAC, synchronous to TX_CLK in MII mode or to the 50MHz reference on XI in RMII mode."+ },+ {+ "number": "5",+ "name": "TXD_2",+ "type": "input",+ "description": "Transmit data bit 2 from the MAC, synchronous to TX_CLK in MII mode (not used in RMII mode, which uses TXD[1:0])."+ },+ {+ "number": "6",+ "name": "TXD_3",+ "type": "input",+ "description": "Transmit data bit 3 from the MAC, synchronous to the rising edge of TX_CLK in MII mode (not used in RMII mode)."+ },+ {+ "number": "7",+ "name": "INT/PWDN",+ "type": "bidirectional",+ "description": "Active-low power-down input by default, or open-drain interrupt output when enabled through register access, with a weak internal pull-up that may need an external pull-up."+ },+ {+ "number": "8",+ "name": "JTAG_TCK",+ "type": "input",+ "description": "JTAG test clock input with a weak internal pullup."+ },+ {+ "number": "9",+ "name": "JTAG_TDO",+ "type": "output",+ "description": "JTAG test data output."+ },+ {+ "number": "10",+ "name": "JTAG_TMS",+ "type": "input",+ "description": "JTAG test mode select input with a weak internal pullup."+ },+ {+ "number": "11",+ "name": "JTAG_TRST",+ "type": "input",+ "description": "Active-low asynchronous JTAG test reset input with a weak internal pullup."+ },+ {+ "number": "12",+ "name": "JTAG_TDI",+ "type": "input",+ "description": "JTAG test data input with a weak internal pullup."+ },+ {+ "number": "13",+ "name": "RD-",+ "type": "bidirectional",+ "description": "Differential receive input pair auto-configured for 100Base-TX or 10Base-T; requires 3.3V bias and serves as the transmit output pair in Auto-MDIX crossover."+ },+ {+ "number": "14",+ "name": "RD+",+ "type": "bidirectional",+ "description": "Differential receive input pair auto-configured for 100Base-TX or 10Base-T; requires 3.3V bias and serves as the transmit output pair in Auto-MDIX crossover."+ },+ {+ "number": "15",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "16",+ "name": "TD-",+ "type": "bidirectional",+ "description": "Differential transmit output pair automatically configured for 10Base-T or 100Base-TX; requires 3.3V bias and serves as the receive input pair in Auto-MDIX mode."+ },+ {+ "number": "17",+ "name": "TD+",+ "type": "bidirectional",+ "description": "Differential transmit output pair automatically configured for 10Base-T or 100Base-TX; requires 3.3V bias and serves as the receive input pair in Auto-MDIX mode."+ },+ {+ "number": "18",+ "name": "PFBIN1",+ "type": "input",+ "description": "Power feedback input fed from PFBOUT in single-supply operation, or connected to a 1.55V external supply in multiple-supply operation, with a 0.1µF capacitor close to the pin."+ },+ {+ "number": "19",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "20",+ "name": "RESERVED",+ "type": "bidirectional",+ "description": "Reserved pin that must be pulled up to AVDD33 through a 2.2kΩ resistor."+ },+ {+ "number": "21",+ "name": "SW_STRAP",+ "type": "input",+ "description": "Connecting an external pull-up resistor to this pin disables software strapping mode during power-up or hardware reset."+ },+ {+ "number": "22",+ "name": "AVDD33",+ "type": "power_in",+ "description": "Analog 3.3V power supply."+ },+ {+ "number": "23",+ "name": "PFBOUT",+ "type": "power_out",+ "description": "Power feedback output for the internal regulator; place 10µF and 0.1µF ceramic capacitors close to the pin and connect to PFBIN1 and PFBIN2 in single-supply operation, otherwise not used."+ },+ {+ "number": "24",+ "name": "RBIAS",+ "type": "input",+ "description": "Bias resistor connection; use a 4.87kΩ 1% resistor from RBIAS to GND."+ },+ {+ "number": "25",+ "name": "CLKOUT",+ "type": "output",+ "description": "Clock output providing 25MHz in MII mode or 50MHz in RMII mode for use by other devices."+ },+ {+ "number": "26",+ "name": "LED_ACT/COL/AN_EN",+ "type": "bidirectional",+ "description": "Configurable LED pin indicating activity (mode 1), collision (mode 2) or duplex (mode 3), which also serves as the AN_EN configuration strap."+ },+ {+ "number": "27",+ "name": "LED_SPEED/AN_1",+ "type": "bidirectional",+ "description": "Speed LED that is ON at 100Mb/s and OFF at 10Mb/s, which also serves as the AN_1 configuration strap."+ },+ {+ "number": "28",+ "name": "LED_LINK/AN_0",+ "type": "bidirectional",+ "description": "Link status LED that is ON for a good link, which also serves as the AN_0 configuration strap."+ },+ {+ "number": "29",+ "name": "RESET",+ "type": "input",+ "description": "Active-low reset input that reinitializes all internal registers when asserted low for at least 1µs."+ },+ {+ "number": "30",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Bidirectional management data signal synchronized to MDC that requires a 2.2kΩ pull-up resistor."+ },+ {+ "number": "31",+ "name": "MDC",+ "type": "input",+ "description": "Management data clock with a maximum rate of 25MHz and no minimum rate, not required to be synchronous to TX_CLK or RX_CLK."+ },+ {+ "number": "32",+ "name": "VDD_IO",+ "type": "power_in",+ "description": "I/O supply of 3.3V, 2.5V, or 1.8V (1.8V for MII mode only)."+ },+ {+ "number": "33",+ "name": "XO",+ "type": "output",+ "description": "Crystal output used only with a crystal; left floating when an oscillator drives XI."+ },+ {+ "number": "34",+ "name": "XI",+ "type": "input",+ "description": "Reference clock input: 25MHz ±50ppm crystal or CMOS oscillator in MII mode, or 50MHz ±50ppm CMOS oscillator in RMII mode."+ },+ {+ "number": "35",+ "name": "IOGND",+ "type": "power_in",+ "description": "I/O ground."+ },+ {+ "number": "36",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "37",+ "name": "PFBIN2",+ "type": "input",+ "description": "Power feedback input fed from PFBOUT in single-supply operation, or connected to a 1.55V external supply in multiple-supply operation, with a 0.1µF capacitor close to the pin."+ },+ {+ "number": "38",+ "name": "RX_CLK",+ "type": "output",+ "description": "MII receive clock providing a 25MHz or 2.5MHz reference derived from the received data stream, depending on speed."+ },+ {+ "number": "39",+ "name": "RX_DV/MII_MODE",+ "type": "bidirectional",+ "description": "Receive data valid indicating valid data on RXD[3:0] (MII) or RXD[1:0] (RMII) independent of carrier sense, with this pin also sampled as the MII_MODE configuration strap."+ },+ {+ "number": "40",+ "name": "CRS/CRS_DV/LED_CFG",+ "type": "bidirectional",+ "description": "Carrier sense asserted high when the receive medium is non-idle in MII mode, or the combined CRS_DV indication in RMII mode, with this pin also serving as the LED_CFG strap."+ },+ {+ "number": "41",+ "name": "RX_ER/AMDIX_EN",+ "type": "bidirectional",+ "description": "Receive error indication asserted on an error symbol in MII or RMII mode, with this pin also serving as the AMDIX_EN configuration strap."+ },+ {+ "number": "42",+ "name": "COL/PHYAD0",+ "type": "bidirectional",+ "description": "Collision detect that is always low in MII full-duplex mode and unused in RMII mode, with this pin also serving as the PHYAD0 address bit (LSB, pulled up)."+ },+ {+ "number": "43",+ "name": "RXD_0/PHYAD1",+ "type": "bidirectional",+ "description": "Receive data bit 0 synchronous to RX_CLK in MII mode or two-bit RXD[1:0] in RMII mode, also serving as PHY address bit PHYAD1 (pulled down)."+ },+ {+ "number": "44",+ "name": "RXD_1/PHYAD2",+ "type": "bidirectional",+ "description": "Receive data bit 1 synchronous to RX_CLK, also serving as PHY address bit PHYAD2 (pulled down)."+ },+ {+ "number": "45",+ "name": "RXD_2/PHYAD3",+ "type": "bidirectional",+ "description": "Receive data bit 2 synchronous to RX_CLK, also serving as PHY address bit PHYAD3 (pulled down)."+ },+ {+ "number": "46",+ "name": "RXD_3/PHYAD4",+ "type": "bidirectional",+ "description": "Receive data bit 3 synchronous to RX_CLK, also serving as PHY address bit PHYAD4 (pulled down)."+ },+ {+ "number": "47",+ "name": "IOGND",+ "type": "power_in",+ "description": "I/O ground."+ },+ {+ "number": "48",+ "name": "VDD_IO",+ "type": "power_in",+ "description": "I/O supply of 3.3V, 2.5V, or 1.8V (1.8V for MII mode only)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin 21 is named SW_STRAP only in the pin diagram (page 4) and its function is described on page 15; ; Pin 25 is named CLKOUT in the pin description table but CLK_OUT in the pin diagram; the table name w; Pins 26-28 and 39-42 are configuration/strap pins with output function (type S,O). They are typed bi"+ ],+ "pages_sent": 32,+ "cost_usd": 0.1918,+ "at": "2026-10-08T06:34:29"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlk110",+ "pages": 104,+ "sha256": "deab430dfd9c08b2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlk110pt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlk110pt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8f4098a73796a02c9e8ee4f642205c06af31cb35058aeb7e813a0618f211620f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}