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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TLK110PT

Texas Instruments · Ethernet Transceivers · LQFP-48(7x7)

TLK110PT from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TX_CLK	output	MII transmit clock providing a 25MHz or 2.5MHz reference depending on speed; unused in RMII mode.
2	TX_EN	input	Transmit enable, presented on the rising edge of TX_CLK and active high, indicating valid data on TXD[3:0] in MII mode or TXD[1:0] in RMII mode.
3	TXD_0	input	Transmit data bit 0 from the MAC, synchronous to TX_CLK in MII mode or to the 50MHz reference on XI in RMII mode.
4	TXD_1	input	Transmit data bit 1 from the MAC, synchronous to TX_CLK in MII mode or to the 50MHz reference on XI in RMII mode.
5	TXD_2	input	Transmit data bit 2 from the MAC, synchronous to TX_CLK in MII mode (not used in RMII mode, which uses TXD[1:0]).
6	TXD_3	input	Transmit data bit 3 from the MAC, synchronous to the rising edge of TX_CLK in MII mode (not used in RMII mode).
7	INT/PWDN	bidirectional	Active-low power-down input by default, or open-drain interrupt output when enabled through register access, with a weak internal pull-up that may need an external pull-up.
8	JTAG_TCK	input	JTAG test clock input with a weak internal pullup.
9	JTAG_TDO	output	JTAG test data output.
10	JTAG_TMS	input	JTAG test mode select input with a weak internal pullup.
11	JTAG_TRST	input	Active-low asynchronous JTAG test reset input with a weak internal pullup.
12	JTAG_TDI	input	JTAG test data input with a weak internal pullup.
13	RD-	bidirectional	Differential receive input pair auto-configured for 100Base-TX or 10Base-T; requires 3.3V bias and serves as the transmit output pair in Auto-MDIX crossover.
14	RD+	bidirectional	Differential receive input pair auto-configured for 100Base-TX or 10Base-T; requires 3.3V bias and serves as the transmit output pair in Auto-MDIX crossover.
15	AGND	power_in	Analog ground.
16	TD-	bidirectional	Differential transmit output pair automatically configured for 10Base-T or 100Base-TX; requires 3.3V bias and serves as the receive input pair in Auto-MDIX mode.
17	TD+	bidirectional	Differential transmit output pair automatically configured for 10Base-T or 100Base-TX; requires 3.3V bias and serves as the receive input pair in Auto-MDIX mode.
18	PFBIN1	input	Power feedback input fed from PFBOUT in single-supply operation, or connected to a 1.55V external supply in multiple-supply operation, with a 0.1µF capacitor close to the pin.
19	AGND	power_in	Analog ground.
20	RESERVED	bidirectional	Reserved pin that must be pulled up to AVDD33 through a 2.2kΩ resistor.
21	SW_STRAP	input	Connecting an external pull-up resistor to this pin disables software strapping mode during power-up or hardware reset.
22	AVDD33	power_in	Analog 3.3V power supply.
23	PFBOUT	power_out	Power feedback output for the internal regulator; place 10µF and 0.1µF ceramic capacitors close to the pin and connect to PFBIN1 and PFBIN2 in single-supply operation, otherwise not used.
24	RBIAS	input	Bias resistor connection; use a 4.87kΩ 1% resistor from RBIAS to GND.
25	CLKOUT	output	Clock output providing 25MHz in MII mode or 50MHz in RMII mode for use by other devices.
26	LED_ACT/COL/AN_EN	bidirectional	Configurable LED pin indicating activity (mode 1), collision (mode 2) or duplex (mode 3), which also serves as the AN_EN configuration strap.
27	LED_SPEED/AN_1	bidirectional	Speed LED that is ON at 100Mb/s and OFF at 10Mb/s, which also serves as the AN_1 configuration strap.
28	LED_LINK/AN_0	bidirectional	Link status LED that is ON for a good link, which also serves as the AN_0 configuration strap.
29	RESET	input	Active-low reset input that reinitializes all internal registers when asserted low for at least 1µs.
30	MDIO	bidirectional	Bidirectional management data signal synchronized to MDC that requires a 2.2kΩ pull-up resistor.
31	MDC	input	Management data clock with a maximum rate of 25MHz and no minimum rate, not required to be synchronous to TX_CLK or RX_CLK.
32	VDD_IO	power_in	I/O supply of 3.3V, 2.5V, or 1.8V (1.8V for MII mode only).
33	XO	output	Crystal output used only with a crystal; left floating when an oscillator drives XI.
34	XI	input	Reference clock input: 25MHz ±50ppm crystal or CMOS oscillator in MII mode, or 50MHz ±50ppm CMOS oscillator in RMII mode.
35	IOGND	power_in	I/O ground.
36	DGND	power_in	Digital ground.
37	PFBIN2	input	Power feedback input fed from PFBOUT in single-supply operation, or connected to a 1.55V external supply in multiple-supply operation, with a 0.1µF capacitor close to the pin.
38	RX_CLK	output	MII receive clock providing a 25MHz or 2.5MHz reference derived from the received data stream, depending on speed.
39	RX_DV/MII_MODE	bidirectional	Receive data valid indicating valid data on RXD[3:0] (MII) or RXD[1:0] (RMII) independent of carrier sense, with this pin also sampled as the MII_MODE configuration strap.
40	CRS/CRS_DV/LED_CFG	bidirectional	Carrier sense asserted high when the receive medium is non-idle in MII mode, or the combined CRS_DV indication in RMII mode, with this pin also serving as the LED_CFG strap.
41	RX_ER/AMDIX_EN	bidirectional	Receive error indication asserted on an error symbol in MII or RMII mode, with this pin also serving as the AMDIX_EN configuration strap.
42	COL/PHYAD0	bidirectional	Collision detect that is always low in MII full-duplex mode and unused in RMII mode, with this pin also serving as the PHYAD0 address bit (LSB, pulled up).
43	RXD_0/PHYAD1	bidirectional	Receive data bit 0 synchronous to RX_CLK in MII mode or two-bit RXD[1:0] in RMII mode, also serving as PHY address bit PHYAD1 (pulled down).
44	RXD_1/PHYAD2	bidirectional	Receive data bit 1 synchronous to RX_CLK, also serving as PHY address bit PHYAD2 (pulled down).
45	RXD_2/PHYAD3	bidirectional	Receive data bit 2 synchronous to RX_CLK, also serving as PHY address bit PHYAD3 (pulled down).
46	RXD_3/PHYAD4	bidirectional	Receive data bit 3 synchronous to RX_CLK, also serving as PHY address bit PHYAD4 (pulled down).
47	IOGND	power_in	I/O ground.
48	VDD_IO	power_in	I/O supply of 3.3V, 2.5V, or 1.8V (1.8V for MII mode only).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-48(7x7)
Category	Interface
Pins	48

CAD (KiCad official)

Symbol: TLK110PT
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: tlk110pt-etched.step / tlk110pt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlk110pt.step / tlk110pt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (104 pp, sha256 deab430dfd9c08b2, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF