component

TLK105RHBR

Public Made by Adom

by adom

Texas Instruments Ethernet Transceivers, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfacetlk105rhbrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

TLK105RHBR

Texas Instruments · Ethernet Transceivers · VQFN-32-EP(5x5)

TLK105RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RXD_3 / PHYAD4 output Receive Data 3 or PHY Address 4; decoded receive data symbol output synchronous to RX_CLK with weak internal pulldown for address configuration.
2 TX_CLK output Transmit Clock providing 25MHz or 2.5MHz reference clock for MII mode; constant phase relationship to REF_CLK.
3 TX_EN input Transmit Enable active-high input indicating valid data on TXD[3:0] in MII or TXD[1:0] in RMII mode with internal pulldown.
4 TXD_0 input Transmit Data 0 input with internal pulldown; synchronous to TX_CLK rising edge in MII mode.
5 TXD_1 input Transmit Data 1 input with internal pulldown; synchronous to TX_CLK rising edge in MII mode.
6 TXD_2 input Transmit Data 2 input with internal pulldown; synchronous to TX_CLK rising edge in MII mode.
7 TXD_3 input Transmit Data 3 input with internal pulldown; synchronous to TX_CLK rising edge in MII mode.
8 INT / PWDN bidirectional Interrupt/Power Down open-drain output with weak internal pullup; default active-low power-down control, configurable as active-low interrupt output via register access.
9 RD- bidirectional Receive Differential Minus pair input accepting 100Base-TX or 10Base-T signaling with 3.3V bias; in Auto-MDIX can serve as transmit output with 16kV HBM ESD protection.
10 RD+ bidirectional Receive Differential Plus pair input accepting 100Base-TX or 10Base-T signaling with 3.3V bias; in Auto-MDIX can serve as transmit output with 16kV HBM ESD protection.
11 TD- bidirectional Transmit Differential Minus pair output configured for 10Base-T or 100Base-TX signaling with 3.3V bias; in Auto-MDIX can serve as receive input with 16kV HBM ESD protection.
12 TD+ bidirectional Transmit Differential Plus pair output configured for 10Base-T or 100Base-TX signaling with 3.3V bias; in Auto-MDIX can serve as receive input with 16kV HBM ESD protection.
13 PFBIN1 power_in Power Feedback Input 1 fed from PFBOUT in single-supply operation or external 1.55V supply in dual-supply operation; 0.1µF bypass capacitor required.
14 AVDD33 power_in Analog 3.3V power supply for AFE and analog circuitry; 10µF and 0.1µF bypass capacitors required close to pin.
15 PFBOUT power_out Power Feedback Output from internal regulator in single-supply operation; requires 10µF and 0.1µF capacitors and connection to PFBIN1/PFBIN2.
16 RBIAS passive Bias Resistor connection point; connect 4.87kΩ 1% resistor from this pin to GND for bias current generation.
17 LED_LINK / AN_0 output LED Link output or Auto-Negotiation Mode select; indicates link status (Mode 1) or link and activity (Mode 2) with internal pullup for full-duplex configuration.
18 RESET input Active-low reset input with internal pullup; minimum 1µs low pulse initiates full device reset and re-latches hardware configuration pins.
19 MDIO bidirectional Management Data I/O bidirectional signal synchronized to MDC for serial management interface; requires external 2.2kΩ pullup resistor.
20 MDC input Management Data Clock input for serial management interface with maximum rate 25MHz; not required synchronous to TX_CLK or RX_CLK.
21 VDD_IO power_in I/O power supply selectable as 3.3V, 2.5V, or 1.8V (MII mode only) for digital I/O logic levels with decoupling capacitor required.
22 XO output Crystal oscillator output for crystal connection; leave floating when external CMOS-level oscillator connected to XI pin.
23 XI input Crystal/Oscillator input accepting 25MHz (MII) or 50MHz (RMII) reference clock with ±50ppm tolerance from external oscillator or crystal resonator.
24 PFBIN2 power_in Power Feedback Input 2 fed from PFBOUT in single-supply operation or external 1.55V supply in dual-supply operation; 0.1µF bypass capacitor required.
25 RX_CLK output Receive Clock output providing 25MHz or 2.5MHz recovered clock derived from received data stream in MII mode; unused in RMII mode.
26 RX_DV / MII_MODE output Receive Data Valid output or Mode select configuration pin; indicates valid data on RXD[3:0] for MII or RXD[1:0] for RMII with internal pulldown; strapping sets MII/RMII mode.
27 CRS / CRS_DV / LED_CFG output Carrier Sense or Carrier Sense/Receive Data Valid output or LED Configuration pin; asserts high when receive medium non-idle in MII/RMII with internal pullup.
28 RX_ER / AMDIX_EN output Receive Error output indicating error symbol detection synchronous to RX_CLK or Auto-MDIX Enable configuration pin with internal pullup.
29 COL / PHYAD0 output Collision Detect output or PHY Address 0; asserts high in half-duplex when both transmit and receive media active; always low in full-duplex with internal pullup.
30 RXD_0 / PHYAD1 output Receive Data 0 or PHY Address 1; decoded receive data output synchronous to RX_CLK with weak internal pulldown for address configuration.
31 RXD_1 / PHYAD2 output Receive Data 1 or PHY Address 2; decoded receive data output synchronous to RX_CLK with weak internal pulldown for address configuration.
32 RXD_2 / PHYAD3 output Receive Data 2 or PHY Address 3; decoded receive data output synchronous to RX_CLK with weak internal pulldown for address configuration.
33 GND power_in Ground and exposed thermal pad on bottom of package; must be soldered for thermal performance; thermal via guidelines: 0.2mm vias, 4 vias minimum, 2mm center-to-center spacing.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Interface
Pins 33

CAD (KiCad official)

  • Symbol: TLK105RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tlk105rhbr-etched.step / tlk105rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlk105rhbr.step / tlk105rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (101 pp, sha256 348238b64fbb769a, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF