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TLIN2029DRBRQ1
Public Made by Adomby adom
Texas Instruments LIN Transceivers, SON-8-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLIN2029DRBRQ1
Texas Instruments · LIN Transceivers · SON-8-EP(3x3)
TLIN2029DRBRQ1 from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RXD | output | Open-drain RXD output reports the state of the LIN bus voltage to the microprocessor. |
| 2 | EN | input | Enable input: high puts the device in normal operation mode and low puts the device in sleep mode. |
| 3 | NC | unconnected | Not connected. |
| 4 | TXD | input | TXD input controls the state of the LIN output and is internally pulled to ground. |
| 5 | GND | power_in | Ground reference for the device. |
| 6 | LIN | bidirectional | LIN bus single-wire transmitter and receiver, with ±45V LIN bus fault protection stated in the features. |
| 7 | VSUP | power_in | Device supply voltage connected to the battery in series with an external reverse blocking diode, operating from 4V to 36V. |
| 8 | NC | unconnected | Not connected. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SON-8-EP(3x3) |
| Category | Interface |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VSUP | -0.3 | 60 | V | parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) | 4 | |
| LIN bus input voltage | VLIN | -60 | 60 | V | parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) | 4 | |
| Logic pin voltage (RXD, TXD, EN) | VLOGIC | -0.3 | 6 | V | parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) | 4 | |
| Ambient temperature range | TA | -40 | 125 | °C | 4 | ||
| Junction temperature range | TJ | -55 | 150 | °C | 4 | ||
| Supply voltage | VSUP | 4 | 48 | V | parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) | 5 | |
| LIN Bus input voltage | VLIN | 0 | 48 | V | parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) | 5 | |
| Logic Pin Voltage (RXD, TXD, EN) | VLOGIC | 0 | 5.25 | V | parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) | 5 | |
| Operational supply voltage | VSUP | 4 | 48 | V | Device is operational beyond the LIN defined nominal supply voltage range. See Figure 6-1 and Figure 6-2 | 5 | |
| Nominal supply voltage | VSUP | 4 | 48 | V | Normal and Standby Modes: ramp VSUP while LIN signal is a 10 kHz square wave with 50 % duty cycle and 36V swing. See Figure 6-1 and Figure 6-2 | 5 | |
| Sleep mode supply voltage | VSUP | 4 | 48 | V | Sleep Mode | 5 | |
| Under voltage VSUP threshold | UVSUP | 2.9 | 3.85 | V | Min is falling edge and Max is rising edge | 5 | |
| Supply current, normal mode, bus dominant | ISUP | 1.2 | 5 | mA | Normal Mode: EN = high, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF (See Figure 6-7) | 5 | |
| Supply current, standby mode, bus dominant | ISUP | 1 | 2.1 | mA | Standby Mode: EN = low, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF (See Figure 6-7) | 5 | |
| Supply current, normal mode, bus recessive | ISUP | 400 | 700 | µA | Normal Mode: EN = high, bus recessive (LIN = VSUP) | 5 | |
| Supply current, standby mode, bus recessive | ISUP | 20 | 35 | µA | Standby Mode: EN = low, bus recessive (LIN = VSUP) | 5 | |
| Supply current, sleep mode 4.0 V to 27 V | ISUP | 9 | 15 | µA | Sleep Mode: 4.0 V < VSUP ≤ 27 V, LIN = VSUP, EN = 0 V, TXD and RXD floating | 5 | |
| Leakage current, high-level (RXD) | IILG | -5 | 0 | 5 | µA | LIN = VSUP, RXD = 5 V | 5 |
| Low level input voltage (TXD) | VIL | -0.3 | 0.8 | V | 6 | ||
| High level input voltage (TXD) | VIH | 2 | 5.5 | V | 6 | ||
| Low level input leakage current (TXD) | IILG | -5 | 0 | 5 | µA | TXD = low | 6 |
| Internal pull-down resistor value (TXD) | RTXD | 125 | 350 | 800 | kΩ | 6 | |
| Receiver center threshold | VBUS_CNT | 0.475 | 0.5 | 0.525 | VSUP | VBUS_CNT = (VIL + VIH)/2. See Figure 6-4, Figure 6-3 | 6 |
| Serial diode LIN term pull-up path | VSERIAL_DIODE | 0.4 | 0.7 | 1 | V | By design and characterization | 6 |
| Internal pull-up resistor to VSUP | RPU-LIN | 20 | 45 | 60 | kΩ | Normal and standby modes | 6 |
| Capacitance of the LIN pin | CLINPIN | 25 | pF | VSUP = 14 V | 6 | ||
| Limiting current | IBUS_LIM | 75 | 120 | 300 | mA | TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω, VSUP = 36 V, VBUSdom < 4.518 V. See Figure 6-6 | 6 |
| Receiver leakage current, recessive | IBUS_PAS_rec2 | -5 | 5 | µA | LIN = VSUP, Driver off; Figure 6-8 | 6 | |
| Leakage current, loss of ground, VSUP = 27 V | IBUS_NO_GND | -1 | 1 | mA | GND = VSUP, VSUP = 27 V, LIN = 0 V; Figure 6-9 | 6 | |
| Leakage current, loss of ground, VSUP ≥ 36 V | IBUS_NO_GND | -1.5 | 1.5 | mA | GND = VSUP, VSUP ≥ 36 V, LIN = 0 V; Figure 6-9 | 6 | |
| Low level input voltage (EN) | VIL | -0.3 | 0.8 | V | 6 | ||
| High level input voltage (EN) | VIH | 2 | 5.5 | V | 6 | ||
| Hysteresis voltage (EN) | VIT | 50 | 500 | mV | By design and characterization | 6 | |
| Low level input current (EN) | IILG | -5 | 0 | 5 | µA | EN = low | 7 |
| Internal pull-down resistor (EN) | REN | 125 | 350 | 800 | kΩ | 7 | |
| Symmetry of receiver propagation delay time | trx_sym | -2 | 2 | µs | Rising edge with respect to falling edge, (trx_sym = trx_pdf, trx_pdr), RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 6-13 and Figure 6-14) | 8 | |
| LIN wakeup time (Minimum dominant time on LIN bus for wakeup) | tLINBUS | 25 | 65 | 150 | µs | See Figure 6-17, Figure 7-2, and Figure 7-3 | 8 |
| Time to clear false wakeup prevention logic | tCLEAR | 8 | 25 | 50 | µs | See Figure 7-3 | 8 |
| Dominant state time out | tDST | 20 | 45 | 80 | ms | 8 | |
| Junction-to-ambient thermal resistance (DRB) | RΘJA | 48.5 | °C/W | DRB (VSON) 8-pin package | 4 | ||
| Junction-to-case (top) thermal resistance (DRB) | RΘJC(top) | 55.5 | °C/W | DRB (VSON) 8-pin package | 4 | ||
| Junction-to-board thermal resistance (DRB) | RΘJB | 22.2 | °C/W | DRB (VSON) 8-pin package | 4 | ||
| Junction-to-top characterization parameter (DRB) | ΨJT | 1.2 | °C/W | DRB (VSON) 8-pin package | 4 | ||
| Junction-to-board characterization parameter (DRB) | ΨJB | 22.2 | °C/W | DRB (VSON) 8-pin package | 4 | ||
| Junction-to-case (bottom) thermal resistance (DRB) | RΘJC(bot) | 4.8 | °C/W | DRB (VSON) 8-pin package | 5 |
CAD (KiCad official)
- Symbol:
TLIN2029DRBRQ1 - Footprint:
Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm - 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tlin2029drbrq1-etched.step/tlin2029drbrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlin2029drbrq1.step/tlin2029drbrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (47 pp, sha256
454f2456d7da4945, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).