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TLIN2022ADRQ1
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Texas Instruments Ethernet ICs, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLIN2022ADRQ1
Texas Instruments · Ethernet ICs · SOIC-14
TLIN2022ADRQ1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RXD1 | output | Channel 1 RXD open-drain output reports the state of the LIN bus voltage, with logic pin voltage (RXD, TXD, EN) limited to 0 to 5.25 V and logic pin output current limited to 8 mA maximum. |
| 2 | EN1 | input | Channel 1 enable input: high puts channel 1 in normal operation mode and low puts it in sleep mode, with logic pin voltage limited to 0 to 5.25 V. |
| 3 | TXD1 | input | Channel 1 TXD input controls the state of the LIN output, with logic pin voltage limited to 0 to 5.25 V. |
| 4 | RXD2 | output | Channel 2 RXD open-drain output reports the state of the LIN bus voltage, with logic pin voltage (RXD, TXD, EN) limited to 0 to 5.25 V and logic pin output current limited to 8 mA maximum. |
| 5 | EN2 | input | Channel 2 enable input: high puts channel 2 in normal operation mode and low puts it in sleep mode, with logic pin voltage limited to 0 to 5.25 V. |
| 6 | NC | unconnected | Not connected. |
| 7 | TXD2 | input | Channel 2 TXD input controls the state of the LIN output, with logic pin voltage limited to 0 to 5.25 V. |
| 8 | GND | power_in | Ground terminal; all voltage values in the datasheet are referenced to this ground. |
| 9 | LIN2 | bidirectional | Channel 2 high-voltage LIN bus single-wire transmitter and receiver, rated for LIN bus input voltage of 0 to 48 V recommended and -60 V to 60 V absolute maximum. |
| 10 | VSUP | power_in | Device supply voltage, connected to the battery through an external reverse blocking diode, with a recommended range of 4 V to 48 V and absolute maximum of -0.3 V to 60 V. |
| 11 | NC | unconnected | Not connected. |
| 12 | NC | unconnected | Not connected. |
| 13 | LIN1 | bidirectional | Channel 1 high-voltage LIN bus single-wire transmitter and receiver, rated for LIN bus input voltage of 0 to 48 V recommended and -60 V to 60 V absolute maximum. |
| 14 | NC | unconnected | Not connected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range (ISO/DIS 17987 Param 10) | VSUP | -0.3 | 60 | V | 5 | ||
| LIN bus input voltage (ISO/DIS 17987 Param 82) | VLIN | -60 | 60 | V | 5 | ||
| Logic pin voltage (RXD, TXD, EN) | VLOGIC | -0.3 | 6 | V | 5 | ||
| Logic pin output current | IO | 8 | mA | 5 | |||
| Junction temperature range | TJ | -55 | 150 | °C | 5 | ||
| Supply voltage | VSUP | 4 | 48 | V | 6 | ||
| LIN Bus input voltage | VLIN | 0 | 48 | V | 6 | ||
| Logic Pin Voltage (RXD, TXD, EN) | VLOGIC | 0 | 5.25 | V | 6 | ||
| Ambient temperature range | TA | -40 | 125 | °C | 6 | ||
| Operational supply voltage (ISO/DIS 17987 Param 10, 53) | VSUP | 4 | 48 | V | Device is operational beyond the LIN defined nominal supply voltage range. See Figure 8-1 and Figure 8-2 | 7 | |
| Nominal supply voltage (ISO/DIS 17987 Param 10, 53) | VSUP | 4 | 48 | V | Normal and Standby Modes: ramp VSUP while LIN signal is a 10 kHZ square wave with 50 % duty cycle and 36V swing. See Figure 8-1 and Figure 8-2 | 7 | |
| Supply voltage, Sleep Mode | VSUP | 4 | 48 | V | Sleep Mode | 7 | |
| Undervoltage VSUP threshold | UVSUP | 2.9 | 3.85 | V | 7 | ||
| Supply current, Normal Mode bus dominant | ISUP | 1.2 | 8.5 | mA | Normal Mode: EN = High, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF | 7 | |
| Supply current, Standby Mode bus dominant | ISUP | 1.1 | 3.75 | mA | Standby Mode: EN = Low, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF | 7 | |
| Supply current, Normal Mode bus recessive | ISUP | 670 | 1600 | µA | Normal Mode: EN = High, Bus Recessive: LIN = VSUP | 7 | |
| Supply current, Standby Mode bus recessive | ISUP | 20 | 40 | µA | Standby Mode: EN = Low, Bus Recessive LIN = VSUP | 7 | |
| Supply current, Sleep Mode (4.0 V < VSUP < 14 V) | ISUP | 10 | 20 | µA | Sleep Mode: 4.0 V < VSUP < 14 V, LIN = VSUP, EN = 0 V, TXD and RXD Floating | 7 | |
| Leakage current, high-level (RXD open drain) | IILG | -5 | 0 | 5 | µA | LIN = VSUP, RXD = 5 V | 7 |
| Low-level input voltage (TXD) | VIL | -0.3 | 0.8 | V | 7 | ||
| High-level input voltage (TXD) | VIH | 2 | 5.25 | V | 7 | ||
| Input threshold voltage, normal modes & selective wake modes (TXD) | VHYS | 50 | 500 | mV | 7 | ||
| Low-level input leakage current (TXD) | IILG | -5 | 0 | 5 | µA | TXD = Low | 7 |
| Internal pull-down resistor value (TXD) | RTXD | 125 | 350 | 800 | kΩ | 7 | |
| Low-level input voltage (EN) | VIL | -0.3 | 0.8 | V | 7 | ||
| High-level input voltage (EN) | VIH | 2 | 5.25 | V | 7 | ||
| Hysteresis voltage (EN) | VHYS | 50 | 500 | mV | By design and characterization | 7 | |
| Low-level input current (EN) | IILG | -5 | 0 | 5 | µA | EN = Low | 7 |
| Internal pull-down resistor (EN) | REN | 125 | 350 | 800 | kΩ | 7 | |
| VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 56) | VSUP_NON_OP | -0.3 | 58 | V | TXD & RXD open LIN = 4 V to 58 V | 8 | |
| Limiting current (ISO/DIS 17987 Param 57) | IBUS_LIM | 75 | 120 | 300 | mA | TXD = 0 V, VLIN = 48 V, RMEAS = 440 Ω, VSUP = 48 V, VBUSdom < 4.518 V | 8 |
| Receiver leakage current, recessive (ISO/DIS 17987 Param 59) | IBUS_PAS_rec2 | -5 | 5 | µA | LIN = VSUP, Driver off; See Figure 8-7 | 8 | |
| Leakage current, loss of ground (ISO/DIS 17987 Param 60) | IBUS_NO_GND | -2 | 2 | mA | GND = VSUP, 0 V ≤ VLIN = 36 V, VSUP = 24 V; See Figure 8-8 | 8 | |
| Leakage current, loss of ground (dominant) | Ileak gnd(dom) | -1 | 1 | mA | GND = open; LIN = dominant; RCommander = 1 kΩ, CL = 1 nF; RResponder = 20 kΩ, CL = 1 nF | 8 | |
| Leakage current, loss of ground (recessive) | Ileak gnd(rec) | -100 | 100 | µA | GND = open; LIN = recessive; RCommander = 1 kΩ, CL = 1 nF; RResponder = 20 kΩ, CL = 1 nF | 8 | |
| LIN recessive high-level input voltage | VIH | 0.47 | 0.6 | VSUP | 7 V ≤ VSUP ≤ 18 V | 8 | |
| LIN dominant low-level input voltage | VIL | 0.4 | 0.53 | VSUP | 7 V ≤ VSUP ≤ 18 V | 8 | |
| Receiver center threshold (ISO/DIS 17987 Param 64) | VBUS_CNT | 0.475 | 0.5 | 0.525 | VSUP | VBUS_CNT = (VBUSdom + VBUSrec)/2; See Figure 8-3 and Figure 8-4 | 8 |
| Hysteresis voltage (SAE J2602) | VHYS | 0.07 | 0.175 | VSUP | VHYS = VIH - VIL; See Figure 8-3 and Figure 8-4 | 8 | |
| Serial diode LIN termination pullup path (ISO/DIS 17987 Param 66) | VSERIAL_DIODE | 0.4 | 0.7 | 1 | V | ISERIAL_DIODE = 10 μA | 8 |
| Pull-up resistor to VSUP (ISO/DIS 17987 Param 71) | RPU | 20 | 45 | 60 | kΩ | Normal and Standby modes | 8 |
| Pull-up current source to VSUP | IRSLEEP | -20 | -2 | µA | Sleep mode, VSUP = 27 V, LIN = GND | 8 | |
| Symmetry of receiver propagation delay time | trs_sym | -2 | 2 | µs | Rising edge with respect to falling edge, (trx_sym = trx_pdf, trx_pdr), RRXD = 2.4 kΩ, CRXD = 20 pF | 11 | |
| LIN wakeup time (minimum dominant time on LIN bus for wakeup) | tLINBUS | 25 | 100 | 150 | µs | See Figure 8-16, Figure 9-2 and Figure 9-3 | 11 |
| Time to clear false wakeup prevention logic (recessive time to clear bus stuck dominant fault) | tCLEAR | 8 | 17 | 50 | µs | See Figure 9-3 | 11 |
| Dominant state time out | tDST | 20 | 34 | 80 | ms | 11 | |
| Mode change delay time | tMODE_CHANGE | 2 | 15 | µs | Time to change from standby mode to normal mode or normal mode to sleep mode through EN pin; See Figure 8-14 and Figure 9-4 | 11 | |
| Junction-to-ambient thermal resistance (SOIC, D) | RΘJA | 82.3 | °C/W | 6 | |||
| Junction-to-case (top) thermal resistance (SOIC, D) | RΘJC(top) | 41.5 | °C/W | 6 | |||
| Junction-to-board thermal resistance (SOIC, D) | RΘJB | 38.4 | °C/W | 6 | |||
| Junction-to-top characterization parameter (SOIC, D) | ΨJT | 8.9 | °C/W | 6 | |||
| Junction-to-board characterization parameter (SOIC, D) | ΨJB | 38.1 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
TLIN2022ADRQ1 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
tlin2022adrq1-etched.step/tlin2022adrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlin2022adrq1.step/tlin2022adrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
ff99c1a0dccb633b, retrieved 2026-10-29, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).